Abstract: A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device.

Abstract: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.

Abstract: A semiconductor device includes a plurality of repeatable circuit cells connectable to one or more conductors providing at least electrical connection to the circuit cells and/or electrical connection between one or more circuit elements in the cells. Each of the circuit cells are configured having gates and active regions forming a grating, wherein, for a given active layer in the device, a width of each active region is substantially the same relative to one another, a spacing between any two adjacent active regions is substantially the same, a width of each gate is substantially the same relative to one another, and a spacing between any two adjacent gates is substantially the same.

Abstract: A non-volatile content addressable memory cell comprises: a first phase change material element, the first phase change material element having one end connected to a match-line; a first transistor, the first transistor having a gate connected to a word-line, a source connected to a true bit-read-write-search-line, and a drain connected to another end of the first phase change material element; a second phase change material element, the second phase change material element having one end connected to the match-line; and a second transistor, the second transistor having a gate connected to the word-line, a source connected to a complementary bit-read-write-search-line, and a drain connected to another end of the second phase change material element.

Abstract: A connection device includes a plurality of re-configurable vias that connect a first metal layer to a second metal layer. An actuating element is disposed between the first metal layer and the second metal layer. The actuating element changes the configuration of the plurality of re-configurable vias to change the plurality of re-configurable vias between a conductive state and a non-conductive state.

Abstract: A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device.

Abstract: A semiconductor device includes a plurality of repeatable circuit cells connectable to one or more conductors providing at least electrical connection to the circuit cells and/or electrical connection between one or more circuit elements in the cells. Each of the circuit cells are configured having gates and active regions forming a grating, wherein, for a given active layer in the device, a width of each active region is substantially the same relative to one another, a spacing between any two adjacent active regions is substantially the same, a width of each gate is substantially the same relative to one another, and a spacing between any two adjacent gates is substantially the same.

Abstract: A circuit and method of controlling integrated circuit power consumption using phase change switches where the phase change switches switchably couple and decouple power sources to logic blocks in response to a programming voltage.

Abstract: A storage cell that may be a memory cell, and an integrated circuit (IC) chip including an array of the memory cells and a method of forming the IC. Each storage cell includes a series connected diode and storage media formed between a top an bottom electrode. The diode is a vertical diode and may be formed in a semiconductor nanowire.

Abstract: Provides a field-enhanced programmable resistance memory cell. In an example embodiment, a resistor includes a resistance structure between a first electrode and a second electrode. The resistance structure includes an insulating dielectric material. The second electrode includes a protrusion extending into the resistance structure. The insulating dielectric material includes a material in which a confined conductive region with a programmable resistance is formable via a conditioning signal.

Abstract: The present invention includes a method for forming a phase change material memory device and the phase change memory device produced therefrom. Specifically, the phase change memory device includes a semiconductor structure including a substrate having a first doped region flanked by a set of second doped regions; a phase change material positioned on the first doped region; and a conductor positioned on the phase change material, wherein when the phase change material is a first phase the semiconductor structure operates as a bipolar junction transistor, and when the phase change material is a second phase the semiconductor structure operates as a field effect transistor.

Abstract: A storage cell, integrated circuit (IC) chip with one or more storage cells that may be in an array of the storage cells and a method of forming the storage cell and IC. Each storage cell includes a stylus, the tip of which is phase change material. The phase change tip may be sandwiched between an electrode and conductive material, e.g., titanium nitride (TiN), tantalum nitride (TaN) or n-type semiconductor. The phase change layer may be a chalcogenide and in particular a germanium (Ge), antimony (Sb), tellurium (Te) (GST) layer.

Abstract: A storage cell that may be a memory cell, and integrated circuit (IC) chip including an array of the memory cells and a method of forming the IC. Each storage cell is formed between a top an bottom electrode. Each cell includes a phase change layer that may be a chalcogenide and in particular a germanium (Ge), antimony (Sb), tellurium (Te) or GST layer. The cell also includes a stylus with the apex of the stylus contacting the GST layer.

Abstract: A structure and method of manufacturing a double-gate integrated circuit which includes forming a laminated structure having a channel layer and first insulating layers on each side of the channel layer, forming openings in the laminated structure, forming drain and source regions in the openings, removing portions of the laminated structure to leave a first portion of the channel layer exposed, forming a first gate dielectric layer on the channel layer, forming a first gate electrode on the first gate dielectric layer, removing portions of the laminated structure to leave a second portion of the channel layer exposed, forming a second gate dielectric layer on the channel layer, forming a second gate electrode on the second gate dielectric layer, doping the drain and source regions, using self-aligned ion implantation, wherein the first gate electrode and the second gate electrode are formed independent of each other.

Abstract: Image systems having three dimensional pixels. Each pixel is comprised of a substrate and a three dimensional stack of color sensors. Wavelength sensitive color reflectors are inserted between the individual color sensors and the semiconductor substrate. Incoming photons are partially converted into an electric charge in a color sensor. The unabsorbed portion is wavelength-selectively reflected to produce additional charge in the color sensor. The transmitted portion passes into a lower color sensor to produce an electric charge in that lower color sensor. The unabsorbed portion is wavelength-selectively reflected by another color reflector to produce additional charge in the lower color sensor. The process repeats for still lower color sensors/color reflectors. The substrate includes logic to interrogate the color sensors. Electrical conductors connect the substrate to the individual color sensors.

Abstract: A multi-bit phase change memory cell including a stack of a plurality of conductive layers and a plurality of phase change material layers, each of the phase change material layers disposed between a corresponding pair of conductive layers and having electrical resistances that are different from one another.

Abstract: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.

Abstract: A connection device includes a plurality of re-configurable vias that connect a first metal layer to a second metal layer. An actuating element is disposed between the first metal layer and the second metal layer. The actuating element changes the configuration of the plurality of re-configurable vias to change the plurality of re-configurable vias between a conductive state and a non-conductive state.