Abstract: An SOI single crystalline chip structure includes an active device layer for having at least one SOI device placed thereon, a buried oxide layer under the active device layer, a metal layer under the buried oxide layer, and a silicon substrate under the metal layer. At least one through hole passing through the buried oxide layer is disposed at a first predetermined position of the buried oxide layer, and at least one concave hole not passing through the buried oxide layer is disposed at a second predetermined position of the bottom surface of the buried oxide layer.

Abstract: An SOI single crystalline chip structure includes an active device layer for having at least one SOI device placed thereon, a buried oxide layer under the active device layer, a metal layer under the buried oxide layer, and a silicon substrate under the metal layer. At least one through hole passing through the buried oxide layer is disposed at a first predetermined position of the buried oxide layer, and at least one concave hole not passing through the buried oxide layer is disposed at a second predetermined position of the bottom surface of the buried oxide layer.

Abstract: A wafer-level method is provided for hot-carrier reliability testing a plurality of MOS transistors formed in a semiconductor wafer. The MOS transistors in the semiconductor wafer are divided into at least three groups, including a first group, a second group, and a third group. A built-in multi-voltage supplier is integrally formed along with the MOS transistors undergoing testing in the same semiconductor wafer. This built-in multi-voltage supplier is devised in such a manner as to divide an input voltage into at least four testing voltages, including a first drain voltage, a second drain voltage, a third drain voltage, and a gate voltage.