Abstract: A variable current gate driver for a transistor includes a first current control device having a first controllable output current. The first current control device is electrically connected between a first bus and an activator of the transistor, and a second current control device having a second controllable output current. The second current control device is electrically connected between the activator of the transistor and a second bus. A controller is operatively connected to the first and second current control devices to control the first and second controllable output currents to control the first and second current control devices to control activation of the transistor via the activator. The controller is operative to control the first and second current control devices to control a slew rate of the transistor.

Abstract: The present disclosure describes tinting techniques in a lens stack assembly for a wearable head mounted display (WHMD). The lens stack assembly includes a waveguide disposed between two lenses, where the two lenses include tints to selectively reduce the amount of ambient light transmitted to the user while not reducing the amount of the display light in the WHMD. In addition, the tinting techniques described herein reduce or eliminate the generation of ghost images resulting from the reflection of outcoupled light from the waveguide away from the user back toward the user.

Abstract: Generalized boot operations for disaggregated, multiple (multi-) semiconductor die (“die”) computing system, and related methods and computer-readable media are disclosed. In exemplary aspects, to provide for generalized boot-up firmware/software for the computing system that does not have to be reconfigured for different configurations of dies in variations of IC packages, a CPU die (or other die) designated as a primary die is configured to perform a discoverable boot process over a side-band discovery bus to discover the other dies present in an IC package of the computing system and to then control their boot-up operations. In this manner, the boot-up firmware/software executed by the primary die to boot-up the computing system can be generalized irrespective of the number of dies and their particular configuration. In this manner, a generalized boot-up firmware/software can be provided to control boot-up operations of the computing system independent of specific dies included.

Abstract: Multi-socket computing system employing a parallelized boot architecture with partially-concurrent processor boot-up operations. In a boot of the multi-socket computing system, a first, master CPU in a master CPU socket is configured to receive a master reset signal indicating a boot-up state. In response, the first, master CPU is configured to execute a first boot program code to perform a first CPU boot-up operation. To parallelize the boot operation of a second, slave CPU in a slave CPU socket, the execution of the first boot program code by the first, master CPU includes communicating a slave boot-up synchronization signal indicating the boot-up state to the second CPU to execute a second boot program code to perform a second CPU boot-up operation. The second CPU starts to perform its CPU boot-up operation partially concurrent with the performance of the CPU boot-up operation to reduce overall boot-up time.

Abstract: A system for adaptively controlling traffic control devices having a traffic signal system, a computing network, a communication system, and a mobile device. The traffic signal system is configured to be in communication with the computing network through the communication system. The mobile device is also configured to be in communication with the computing network through the communication system. Then the computing network adaptively controls the traffic signal system using a location of the mobile device.

Abstract: Multi-socket computing system employing a parallelized boot architecture with partially-concurrent processor boot-up operations. In a boot of the multi-socket computing system, a first, master CPU in a master CPU socket is configured to receive a master reset signal indicating a boot-up state. In response, the first, master CPU is configured to execute a first boot program code to perform a first CPU boot-up operation. To parallelize the boot operation of a second, slave CPU in a slave CPU socket, the execution of the first boot program code by the first, master CPU includes communicating a slave boot-up synchronization signal indicating the boot-up state to the second CPU to execute a second boot program code to perform a second CPU boot-up operation. The second CPU starts to perform its CPU boot-up operation partially concurrent with the performance of the CPU boot-up operation to reduce overall boot-up time.

Abstract: A system for adaptively controlling traffic control devices having a traffic signal system, a computing network, a communication system, and a mobile device. The traffic signal system is configured to be in communication with the computing network through the communication system. The mobile device is also configured to be in communication with the computing network through the communication system. Then the computing network adaptively controls the traffic signal system using a location of the mobile device.

Abstract: An optical apparatus includes a light emitting apparatus and a host apparatus. The light emitting apparatus includes a housing extending in a first direction, a light emitting device mounted in the housing, an optical connector including a first optical connection part provided at one end of the housing, and an electrical connector including a first electrical connection part provided at one end of the housing and receiving a voltage to drive the light emitting device. The host apparatus includes a host optical connector including a second optical connection part which faces the first optical connection part and is optically coupled thereto, a host electrical connector including a second electrical connection part facing the first electrical connection part and being electrically connected to the first electrical connection part, and a host board mounting the host optical connector and the host electrical connector thereon.

Abstract: A slew rate controllable system for powering an electric machine. The system may include a plurality of power transistors operable for converting a direct current (DC) input into an alternating current (AC) output suitable for electrically powering the electric machine. The system may further include a gate drive system operable for controlling a slew rate associated with transitioning the power transistors between the opened and closed states.

Abstract: A variable current gate driver for a transistor includes a first current control device having a first controllable output current. The first current control device is electrically connected between a first bus and an activator of the transistor, and a second current control device having a second controllable output current. The second current control device is electrically connected between the activator of the transistor and a second bus. A controller is operatively connected to the first and second current control devices to control the first and second controllable output currents to control the first and second current control devices to control activation of the transistor via the activator. The controller is operative to control the first and second current control devices to control a slew rate of the transistor.

Abstract: Generalized boot operations for disaggregated, multiple (multi-) semiconductor die (“die”) computing system, and related methods and computer-readable media are disclosed. In exemplary aspects, to provide for generalized boot-up firmware/software for the computing system that does not have to be reconfigured for different configurations of dies in variations of IC packages, a CPU die (or other die) designated as a primary die is configured to perform a discoverable boot process over a side-band discovery bus to discover the other dies present in an IC package of the computing system and to then control their boot-up operations. In this manner, the boot-up firmware/software executed by the primary die to boot-up the computing system can be generalized irrespective of the number of dies and their particular configuration. In this manner, a generalized boot-up firmware/software can be provided to control boot-up operations of the computing system independent of specific dies included.

Abstract: A weeding device provides leverage for pulling a deeply-rooted plant from soil without requiring excessive foot pressure for operation. A handle is attached to a weeder head having a first fork extending away from the end of the handle. A rotating jaw is mounted to the weeder head, and has a second fork displaced from the first fork when the second fork are parallel. The weeding device has a step for applying foot pressure to insert the first and second forks in the soil prior. A lever extension of the rotating jaw on an opposite side of the handle contacts the soil when the forks are fully inserted in the soil, and as the handle is rotated toward the soil a tip of the second fork inclines toward a tip of the first fork to close the first fork and the second fork around a plant.

Abstract: Computing systems employing a secure boot processing system that disallows in-bound access when performing immutable boot-up tasks for enhanced security, and related methods and computer-readable media. The computing system includes a secure boot processing system that performs boot-up operations. The secure boot processing system includes an immutable secure boot subsystem that performs lower-level, immutable boot-up tasks that are critical to the security of the computing system. To prevent or mitigate external unauthorized access to the immutable secure boot subsystem that could compromise the security of the computing system, the immutable secure boot controller is configured to disallow external, inbound access to boot system interface of the secure boot processing system to perform immutable boot-up tasks.

Abstract: Apparatuses, systems, and methods for distributing a global counter value in a multi-socket SoC complex. In exemplary aspects, an apparatus comprises a first system-on-a-chip (SoC) in a first socket and a second SoC in a second socket. The apparatus further comprises a reset circuit coupled to the first SoC and the second SoC, a reset synchronization circuit coupled to the reset circuit, the first SoC, and the second SoC, and a global counter clock signal coupled to the reset synchronization circuit, the first SoC, and the second SoC. The reset synchronization circuit is configured to generate a global counter reset signal in response to a reset signal received from the reset circuit and to distribute the global counter reset signal to the first SoC and the second SoC substantially simultaneously.

Abstract: Apparatuses, systems, and methods for collecting and managing data from a plurality of sensors across a system-on-a-chip (SoC). In exemplary aspects, an apparatus comprises an external memory and a system management processor coupled to external memory and configured to be programmed by external memory. The apparatus further comprises a plurality of sensor circuits coupled to the system management processor and the external memory and configured to be programmed by the external memory. The external memory stores configuration information for programming each of the plurality of sensor circuits to collect and provide data concurrently with each of the others of the plurality of sensor circuits to be analyzed by a management firmware program and a management firmware program configured to analyze data received at the system management processor from the plurality of sensor circuits. The external memory is configured to program the system management processor and the plurality of sensor circuits.

Abstract: Multi-socket computing system employing a parallelized boot architecture with partially-concurrent processor boot-up operations. In a boot of the multi-socket computing system, a first, master CPU in a master CPU socket is configured to receive a master reset signal indicating a boot-up state. In response, the first, master CPU is configured to execute a first boot program code to perform a first CPU boot-up operation. To parallelize the boot operation of a second, slave CPU in a slave CPU socket, the execution of the first boot program code by the first, master CPU includes communicating a slave boot-up synchronization signal indicating the boot-up state to the second CPU to execute a second boot program code to perform a second CPU boot-up operation. The second CPU starts to perform its CPU boot-up operation partially concurrent with the performance of the CPU boot-up operation to reduce overall boot-up time.

Abstract: Apparatuses, systems, and methods for distributing a global counter value in a multi-socket SoC complex. In exemplary aspects, an apparatus comprises a first system-on-a-chip (SoC) in a first socket and a second SoC in a second socket. The apparatus further comprises a reset circuit coupled to the first SoC and the second SoC, a reset synchronization circuit coupled to the reset circuit, the first SoC, and the second SoC, and a global counter clock signal coupled to the reset synchronization circuit, the first SoC, and the second SoC. The reset synchronization circuit is configured to generate a global counter reset signal in response to a reset signal received from the reset circuit and to distribute the global counter reset signal to the first SoC and the second SoC substantially simultaneously.

Abstract: The disclosure provides methods of producing a salt product which includes starting with a quantity of salt, placing the salt under an infrared light for a period of time, exposing the salt to sunlight for a period of time, exposing the salt to maifan stones for a period of time, and roasting the salt while being contained in clay pots that are surrounded with elements such as apatite, tourmaline, germanium, maifan (barley stone), volcanic rocks, titanium, and illite at high temperature for a period of time. The salt may include sea salt.

Abstract: A method for forming a fence includes forming first and second feet each having at least two extensions thereon, wherein at least three extensions are spaced apart and parallel to each other; forming a frame having first, second and third elongated posts, wherein the first elongated post is below the extensions projecting from the first and second feet, wherein the third elongated post is positioned above the first and second posts, and wherein the second support post is positioned between the first and third elongated posts; and forming a wire mesh on the frame and welded to the three elongated posts.