Abstract: A package comprising a first substrate, a first integrated device coupled to the first substrate, a second substrate coupled to the first substrate through at least a plurality of solder interconnects, and an encapsulation layer located between the first substrate and the second substrate. The first substrate comprises at least one first dielectric layer; and a first plurality of interconnects, wherein the first plurality of interconnects include a first plurality of post interconnects. The second substrate comprises at least one second dielectric layer; and a second plurality of interconnects, wherein the second plurality of interconnects include a second plurality of post interconnects.

Abstract: A substrate includes a core layer and a bridge die within the core layer. The bridge die includes first contacts and second contacts. The first contacts are electrically connected to the second contacts via conductive traces of the bridge die. The substrate also includes at least one dielectric layer on a surface of the core layer and the bridge die, third contacts on a surface of the at least one dielectric layer and electrically connected to the first contacts, and fourth contacts on the surface of the at least one dielectric layer and electrically connected to the second contacts.

Abstract: In an aspect, a substrate for an integrated circuit (IC) package includes a first dielectric layer, a first metallization layer on a first surface of the first dielectric layer and including a first pad structure and a first trace structure, a second metallization layer on a second surface of the first dielectric layer and including a second pad structure and a second trace structure, a second dielectric layer on the second surface of the first dielectric layer, and a third metallization layer on a second surface of the second dielectric layer and having a third pad structure. The substrate further includes a conductive stud coupled to the second pad structure and a second via structure embedded in the second dielectric layer. The second via structure has a first end coupled to the conductive stud and a second end coupled to the third pad structure.

Abstract: A device includes a substrate that includes a first layer stack including metal and dielectric layers. A first metal layer includes first contacts disposed in a first region and to electrically connect to an IC device, via pads disposed in a second region offset along a first direction, and traces electrically connecting the first contacts and the via pads. The substrate includes, in both regions, a solder resist layer disposed on the first metal layer and a first dielectric layer. The solder resist layer defines openings to the first contacts and the via pads. The substrate includes a second layer stack disposed on the second region and including a second metal layer on the solder resist layer opposite the first layer stack. The second metal layer defines second contacts to electrically connect to second IC device(s) and includes conductive vias between the via pads and the second contacts.

Abstract: A substrate comprising at least one dielectric layer, and a plurality of interconnects located at least partially in the at least one dielectric layer, wherein the plurality of interconnects include a plurality of via interconnects, and wherein the plurality of via interconnects include a first via interconnect comprising a first via wall that is approximately vertical.

Abstract: A substrate comprising a core layer, at least one first dielectric layer coupled to a first surface of the core layer, at least one second dielectric layer coupled to a second surface of the core layer, a plurality of interconnects located at least partially in the at least one first dielectric layer; a region comprising a plurality of block interconnects of an interconnect block; and a solder resist layer coupled to the at least one first dielectric layer.

Abstract: A package comprising an integrated device; and a substrate coupled to the integrated device through at least a plurality of solder interconnects. The substrate comprises a core layer comprising a cavity; a region comprising a passive component block located at least partially in the cavity of the core layer, wherein the passive component block comprises a first passive device and a second passive device; at least one dielectric layer coupled to the core layer; and a plurality of interconnects located at least partially in the at least one dielectric layer.

Abstract: Hybrid package substrates employing film metallization layers with outer pre-impregnated (PPG) region(s) to support high density bump and wire bond connections for respective bump and wire bond connected dies in the IC package, and related hybrid integrated circuit (IC) packages and fabrication methods are disclosed. The package substrate includes film metallization layers of a softer, flexible material that can more easily be patterned to support formation of high density, reduced pitch metal interconnects to support finer bump pitch connections to a bottom, first die(s) in a die region of the package substrate. The package substrate also includes one or more PPG regions a PPG metallization layer(s) adjacent to the die region of the package substrate that reinforces the film metallization layers and also supports the formation of wire bond pads for wire bond connections to an upper, second die(s) in the hybrid IC package.

Abstract: A substrate comprising: a core layer comprising a cavity; an embedded passive device located at least partially in the cavity of the core layer, wherein the embedded passive device comprises a plurality of pad interconnects; a polyimide layer coupled to a surface of the embedded passive device; at least one dielectric layer coupled to the core layer; and a plurality of interconnects located at least partially in the at least one dielectric layer.

Abstract: A device comprising a first package and a second package coupled to the first package through a first plurality of solder interconnects. The first package includes a first substrate comprising at least one first dielectric layer and a first plurality of interconnects, and a first integrated device coupled to the first substrate. The second package includes a second substrate comprising at least one second dielectric layer and a second plurality of interconnects, a second integrated device coupled to a first surface of the second substrate, a third integrated device coupled to the first surface of the second substrate through a second plurality of solder interconnects and a first plurality of channel interconnects coupled to the first surface of the second substrate, wherein the first plurality of channel interconnects is located between solder interconnects from the second plurality of solder interconnects.

Abstract: A device includes a substrate including first conductors connecting contacts on a first side of the substrate to contacts on a second side of the substrate. The first conductors include metal lines arranged in metal layers separated from one another by dielectric layers and conductive vias interconnecting the metal lines. The substrate also includes second conductors connecting contacts on the first side of the substrate to contacts on the first side of the substrate to define conductive paths between a first die and a second die. The second conductors include metal lines arranged in metal layers that are separated from one another by dielectric layers and conductive vias interconnecting the metal lines of the second conductors. At least one metal layer of the second conductors is devoid of the metal lines of the first conductors.

Abstract: Disclosed are devices in which a die, such as a system-on-chip (SoC) die is attached to an interposer with a mold. Unlike convention devices, the contact area for adhesion is increased by providing vertical surfaces in addition to lateral surfaces for attachment. In so doing, possibility of delamination is decreased significantly.

Abstract: Package substrate with metallization layer(s) that includes an additional metal pad layer to facilitate reduced via size for reduced bump pitch, and related integrated circuit (IC) packages and fabrication methods. An additional metal pad(s) is provided in an insulating layer of a metallization layer(s) of the package substrate in which a via(s) is formed to reduce vertical connectivity distance between metal interconnects in adjacent metallization layers electrically coupled together by the via. This can reduce the aspect ratio and size of the via thereby allowing metal interconnects that are electrically coupled to the via to also be reduced in size (e.g., width) while still supporting an aligned, low resistance connection between the via(s) and the metal interconnects. Being able to reduce the size (e.g., width) of the metal interconnects can reduce bump pitch of the package substrate, which can facilitate a higher density of die/bump connections to the package substrate.

Abstract: Disclosed is a stack via structure in which a plurality of vias are stacked over each other. At least one via is a via that has a recess formed from a top surface thereof. Another via above the via is formed such that a bottom portion of the another via is in the recess of the via. In this way, no capture pad is needed between the via and the another via. Also, contact area between the via and the another via is enhanced.

Abstract: In an aspect, an apparatus includes a package. The package includes a substrate, a plurality of components located on a top surface of the substrate, a plurality of ball pads located on a bottom surface of the substrate, a plurality of balls, and a plurality of test pads located on the bottom surface of the substrate. Individual balls of the plurality of balls are attached to individual ball pads of the plurality of ball pads.

Abstract: In an aspect, a substrate includes a core that includes a core dielectric and a first conductive pattern on a first surface of the core dielectric, and a first metallization structure over the first surface of the core dielectric. The first metallization structure includes a first dielectric, and the first dielectric has a first opening formed therein. The substrate further includes a first electronic component disposed in the first opening of the first dielectric, and a first adhesive layer coupling the first electronic component with the core.

Abstract: In an aspect, a substrate is disclosed that includes an electronic component including a lower planar surface having one or more electronic component terminals, a core having an upper planar surface facing the lower planar surface of the electronic component; a patterned metallization layer over the upper planar surface of the core, wherein the patterned metallization layer is connected to the one or more electronic component terminals at the lower planar surface of the electronic component; one or more dielectric layers disposed over the upper planar surface of the core; and a cavity formed within the one or more dielectric layers, wherein the electronic component is located in the cavity and over the upper planar surface of the core.

Abstract: In an aspect, an electronic device is disclosed that includes a substrate comprising a core having an upper planar surface and a lower planar surface, wherein the core includes a cavity extending through the core; an electronic component at least partially disposed in the cavity, wherein the electronic component has an upper planar surface having one or more electronic component terminals; a first cured resin layer, wherein the upper planar surface of the electronic component is at least partially embedded in the first cured resin layer at least at an upper portion of the cavity; and an upper metallization structure disposed over the upper planar surface of the core, wherein the upper metallization structure is configured to provide one or more conductive paths from the one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure.

Abstract: A package comprising a package substrate and a first integrated device coupled to the package substrate through a first plurality of solder interconnects. The package substrate comprises a bridge and/or an interposer, an encapsulated portion, a first metallization portion coupled to a first surface of the encapsulated portion, and a second metallization portion coupled to a second surface of the encapsulated portion. The encapsulated portion comprises a first interconnection portion block, a second interconnection portion block, a plurality of pillar interconnects, and an encapsulation layer encapsulating the first interconnection portion block, the second interconnection portion block, and the plurality of pillar interconnects. The plurality of pillar interconnects comprises a first plurality of pillar interconnects coupled to the first interconnection portion block and a second plurality of pillar interconnects coupled to the second interconnection portion block.

Abstract: A package comprising a package substrate and a first integrated device coupled to the package substrate through a first plurality of solder interconnects. The package substrate comprises an encapsulated portion, a first metallization portion coupled to a first surface of the encapsulated portion, and a second metallization portion coupled to a second surface of the encapsulated portion. The encapsulated portion comprises a first interconnection portion block, a second interconnection portion block, a plurality of pillar interconnects, and an encapsulation layer at least partially encapsulating the first interconnection portion block, the second interconnection portion block, and the plurality of pillar interconnects. The plurality of pillar interconnects comprises a first plurality of pillar interconnects coupled to the first interconnection portion block and a second plurality of pillar interconnects coupled to the second interconnection portion block.