Patents by Inventor Hong-Chi Yu

Hong-Chi Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240120300
    Abstract: A chip package which includes a glass fiber substrate made of FR-4 fiberglass is provided. The chip package further includes a substrate pad which is a stacked metal structure with a certain thickness and composed of a nickel layer, a palladium layer, and a gold layer, or a nickel layer and a gold layer stacked over at least one first circuit layer in turn. A total thickness of the substrate pad is 3.15-5.4 ?m. The glass fiber substrate and the substrate pad can bear positive pressure generated during wire bonding. Thereby at least one solder joint is formed on the substrate pad precisely and integrally. This helps reduction in material cost for manufacturers.
    Type: Application
    Filed: September 8, 2023
    Publication date: April 11, 2024
    Inventors: HONG-CHI YU, CHUN-JUNG LIN, RUEI-TING GU
  • Publication number: 20240096758
    Abstract: A chip package having die pads with protective layers is provided. At least one protective layer is covering and arranged at a peripheral zone of at least one die pad for minimizing area of the die pad exposed outside as well as shielding and protecting the peripheral zone of the die pad. A weld zone of the die pad is not covered by the protective layer so that the weld zone of the die pad is exposed. In a crossed-over state, one of bonding wires crossing one of the die pads with a corresponding connection pad of a carrier plate will not get across a second upper space defined by the weld zone of the rest of the die pads. Thereby the one of the bonding wires can be more isolated by the protective layers on the peripheral zones of the rest of the die pads.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 21, 2024
    Inventors: HONG-CHI YU, CHUN-JUNG LIN, RUEI-TING GU
  • Publication number: 20240088057
    Abstract: A chip package with at least one electromagnetic interference (EMI) shielding layer and at least one ground wire and a method of manufacturing the same are provided. The chip package includes a chip package unit, at least one EMI shielding layer, and at least one ground wire. The ground wire which consists of a first end and a second end opposite to the first end is inserted through the EMI shielding layer and a first insulating layer of the chip package unit. The first end is electrically connected with the EMI shielding layer while the second end of the ground wire is electrically connected with at least one grounding end of at least one first circuit layer of the chip package unit for protection against static electricity. Thereby malfunction of an electronic system with semiconductor chips due to static electricity can be avoided.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 14, 2024
    Inventors: HONG-CHI YU, CHUN-JUNG LIN, RUEI-TING GU
  • Publication number: 20240063138
    Abstract: A chip package having four sides provided with electromagnetic interference (EMI) shielding layers correspondingly and a method of manufacturing the same are provided. The four EMI shielding layers are made of metals, located on four lateral sides of the chip package, and completely covering four lateral sides of a substrate and four lateral sides of an insulating layer to prevent at least one first circuit layer, at least one second circuit layer, and at least one chip from electromagnetic interference. Moreover, the EMI shielding layers help to improve heat dissipation efficiency of the first circuit layer, the second circuit layer, and the chip.
    Type: Application
    Filed: July 27, 2023
    Publication date: February 22, 2024
    Inventors: HONG-CHI YU, CHUN-JUNG LIN, RUEI-TING GU
  • Publication number: 20240047375
    Abstract: A chip package with an electromagnetic interference shielding layer and a method of manufacturing the same are provided. The chip package includes a substrate, at least one first circuit layer, at least one second circuit layer, at least one chip, a first insulating layer, and at least one electromagnetic interference shielding layer. The electromagnetic interference shielding layer is made of metals and covering a first surface of the first insulating layer completely for preventing the respective first circuit layers, the respective second circuit layers, and the respective chips from external electromagnetic interference (EMI).
    Type: Application
    Filed: July 27, 2023
    Publication date: February 8, 2024
    Inventors: HONG-CHI YU, CHUN-JUNG LIN, RUEI-TING GU
  • Publication number: 20240030124
    Abstract: A chip package unit, a method of manufacturing the same, and package structure formed by stacking the same are provided. At least one first connecting pad, at least one second connecting pad, and at least one third connecting pad of a flexible printed circuit (FPC) board in the chip package unit are electrically connected with one another by circuit of the FPC board. At least one die pad disposed on a front surface of a chip is electrically connected with the first connecting pad first and then electrically connected with the outside by the second connecting pad or the third connecting pad. Thereby the chip of the chip package unit can be electrically connected with the outside by the front surface or a back surface thereof. Therefore, not only production is reduced due to simplified production process and energy saved, volume of the package structure is also reduced.
    Type: Application
    Filed: July 11, 2023
    Publication date: January 25, 2024
    Inventors: HONG-CHI YU, CHUN-JUNG LIN, RUEI-TING GU
  • Publication number: 20240021552
    Abstract: A chip package unit, a method of manufacturing the same, and a package structure formed by stacking the same are provided. The chip package unit is formed by cutting of a wafer separately. The chip package unit includes a chip, a first redistribution layer (RDL), a second RDL, and at least one first circuit layer. The first circuit layer is electrically connected with and disposed between a first conductive circuit and a second conductive circuit. The first circuit layer is located at least one first lateral side of the chip, at least one second lateral side of the first RDL, and at least one third lateral side of the second RDL. The chip can be electrically connected with the outside by the first conductive circuit or the second conductive circuit. Thereby manufacturing process is simplified and manufacturing cost is further reduced.
    Type: Application
    Filed: July 10, 2023
    Publication date: January 18, 2024
    Inventors: HONG-CHI YU, CHUN-JUNG LIN, RUEI-TING GU
  • Publication number: 20230411363
    Abstract: A multi-layer stacked chip package is provided. A first substrate, a first circuit layer, a first chip, and a first insulation layer form a lower layer chip package while a second substrate, a second circuit layer, a second chip, and a second insulation layer form an upper layer chip package. The upper layer chip package is stacked over the lower layer chip package so that the multi-layer stacked chip package is formed by such stacking mode. One of the at least two chips is used to operate the rest chips or computing functions of the respective chips are combined to increase overall computing performance.
    Type: Application
    Filed: June 15, 2023
    Publication date: December 21, 2023
    Inventors: HONG-CHI YU, CHUN-JUNG LIN, RUEI-TING GU
  • Publication number: 20230411317
    Abstract: A chip package which includes a chip, at least one first dielectric layer, at least one second dielectric layer, at least one conductive circuit, and at least one third dielectric layer is provide. The conductive circuit is formed by highly concentrated silver paste or copper paste filled in at least one first groove of the first dielectric layer and at least one second groove of the second dielectric layer while at least one die pad of the chip is electrically connected with the conductive circuit for improving electrical conduction efficiency of the conductive circuit. Moreover, at least one die-pad bump is formed in the first groove, arranged at and electrically connected with a surface of the die pad for protecting of the die pad.
    Type: Application
    Filed: June 8, 2023
    Publication date: December 21, 2023
    Inventors: HONG-CHI YU, CHUN-JUNG LIN, RUEI-TING GU
  • Publication number: 20230395538
    Abstract: A chip package with higher bearing capacity in wire bonding is provided. The chip package includes at least one conductive circuit which is a structure with a thickness ranging from 4.5 ?m to 20 ?m. Thereby a structural strength of the conductive circuit is improved and able to stand a positive pressure generated in wire bonding or formation of a first bonding point. Thus at least one internal circuit of a chip will not be damaged by the positive pressure and allowed to pass through an area under the first bonding point or arrange under the first bonding point. A problem of increased cost at manufacturing end caused by the internal circuit redesign of the chip can be solved effectively. This is beneficial to cost reduction at manufacturing end.
    Type: Application
    Filed: June 6, 2023
    Publication date: December 7, 2023
    Inventors: HONG-CHI YU, CHUN-JUNG LIN, RUEI-TING GU
  • Publication number: 20230395453
    Abstract: A chip package and a method of manufacturing the same are provided. The chip package includes at least one insulating protective layer disposed on a periphery of a surface of a seed layer correspondingly. A plurality of insulating protective layers is arranged at the seed layer of a plurality of rectangular chips of a wafer and located corresponding to a plurality of dicing streets. Thereby cutting tools only cut the insulating protective layer, without cutting a thick metal layer during cutting process. The insulating protective layer is formed on a periphery of the thick metal layer of the chip package after the cutting process.
    Type: Application
    Filed: June 6, 2023
    Publication date: December 7, 2023
    Inventors: HONG-CHI YU, CHUN-JUNG LIN, RUEI-TING GU
  • Publication number: 20230395537
    Abstract: A bump of a chip package with higher bearing capacity in wire bonding is provided. The at least one bump of the chip package is a metal stacked member with a certain thickness. An overall thickness of the bump is 4.5-20 ?m. Thereby a structural strength of the bump is improved and thus able to bear positive pressure generated in wire bonding or formation of a first bonding point. Thus at least one internal circuit of a chip will not be damaged by the positive pressure and allowed to pass through an area under at least one die pad or arrange under the die pad of the chip. Thereby increased cost problem caused by internal circuit redesign of the chip can be solved and this helps to reduce cost at manufacturing end.
    Type: Application
    Filed: June 6, 2023
    Publication date: December 7, 2023
    Inventors: HONG-CHI YU, CHUN-JUNG LIN, RUEI-TING GU
  • Patent number: 11245688
    Abstract: The present disclosure relates to a device authentication method as a procedure designed for authenticity of an apparatus. A connecting apparatus to be authenticated and an authentication box are connected to a trusted network through which authentication information is received by the connecting apparatus. The connecting apparatus is electrically connected to a non-trusted network through which the connecting apparatus and an intermediary server are electrically connected with each other; a virtual hub network is created by the intermediary server and electrically connected to both the authentication box and the connecting apparatus such that the connecting apparatus is authenticated by authentication box based on the authentication information.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: February 8, 2022
    Assignee: WALTON ADVANCED ENGINEERING INC.
    Inventors: Hong Chi Yu, Mao Ting Chang
  • Patent number: 11036893
    Abstract: The present disclosure relates to a data retention method which ensures security of classified information in design. The data retention method comprises steps as follows: a data plug of a dedicated storage module is inserted into a data socket of an encryption module and a locking element of a lock fastener module is fixed at a locking hole on the dedicated storage module; the encryption module and the dedicated storage module are electrically connected to each other through the data socket; an external component of the encryption module is electrically connected to an external device such that classified information (saved or to be saved) is encrypted or decrypted between the external device and a storage element of the dedicated storage module by an encryption component of the encryption module during data exchanges.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: June 15, 2021
    Assignee: WALTON ADVANCED ENGINEERING INC.
    Inventors: Hong Chi Yu, Mao Ting Chang
  • Publication number: 20210157138
    Abstract: The present application relates to a storage device with a message projection function such that image light from an image generation unit of an information outlet, which has been electrically connected with an dedicated storage module, passes through and is diffused by a diffusion unit for projection of a created virtual image on a surface.
    Type: Application
    Filed: October 26, 2020
    Publication date: May 27, 2021
    Applicant: WALTON ADVANCED ENGINEERING INC.
    Inventors: Hong Chi YU, Mao Ting CHANG
  • Publication number: 20210036996
    Abstract: The present disclosure relates to a method for connections of peer devices with features: a first peer box produces authentication information which will be saved in an authentication storage module and comprises a network location and an encryption key of the first peer box; the authentication storage module is electrically connected with a second peer box such that both the network location and the encryption key of the first peer box are received by the second peer box through the authentication information; both the network location and the encryption key of the second peer box are added into the authentication information in the authentication storage module from the second peer box; finally, the authentication storage module is electrically connected with a third peer box such that both the network locations and the encryption keys of the former peer boxes are received by the third peer box through the authentication information.
    Type: Application
    Filed: October 16, 2019
    Publication date: February 4, 2021
    Applicant: WALTON ADVANCED ENGINEERING INC.
    Inventors: Hong Chi YU, Mao Ting CHANG
  • Publication number: 20200265434
    Abstract: The present disclosure relates to a transaction authentication method in which a process for transaction safety is created: a consumption confirmation is sent to an authentication box from a transaction platform on which a user has a customer behavior through the internet; the authentication box notifies the user based on a default configuration; the user replies the authentication box by confirmed information; a dedicated confirmation code is replied to the transaction platform from the authentication box and the customer behavior of the user is approved by the transaction platform.
    Type: Application
    Filed: March 28, 2019
    Publication date: August 20, 2020
    Applicant: WALTON ADVANCED ENGINEERING INC.
    Inventors: Hong Chi YU, Mao Ting CHANG
  • Publication number: 20200264793
    Abstract: The present disclosure relates to a method to change the capacity of a storage device through which the capacity of an external storage device is increased as required without payment of extra charges in the beginning. In the method, a standard capacity sector only is accessed through a data access interface; then, an authorization code for dedicated unlock software is entered for electrical connection to an authorization module through a data access interface and one capacity expansion sector accessed based on the authorization code; finally, both a standard capacity sector and a capacity expansion sector are accessed through the data access interface.
    Type: Application
    Filed: March 28, 2019
    Publication date: August 20, 2020
    Applicant: WALTON ADVANCED ENGINEERING INC.
    Inventors: Hong Chi YU, Mao Ting CHANG
  • Publication number: 20200267140
    Abstract: The present disclosure relates to a device authentication method as a procedure designed for authenticity of an apparatus. A connecting apparatus to be authenticated and an authentication box are connected to a trusted network through which authentication information is received by the connecting apparatus. The connecting apparatus is electrically connected to a non-trusted network through which the connecting apparatus and an intermediary server are electrically connected with each other; a virtual hub network is created by the intermediary server and electrically connected to both the authentication box and the connecting apparatus such that the connecting apparatus is authenticated by authentication box based on the authentication information.
    Type: Application
    Filed: May 8, 2019
    Publication date: August 20, 2020
    Applicant: WALTON ADVANCED ENGINEERING INC.
    Inventors: Hong Chi YU, Mao Ting CHANG
  • Patent number: 10693960
    Abstract: A data exchange guide device and an execution method thereof provided in the present disclosure are characterized that a processing program, which is executed by an electronic device connected with a connection interface, is able to read private key information, access a tabulation of remote shared data from an existing network available to the electronic device, and display the tabulation on a graphic user interface. Furthermore, a data exchange guide device and an execution method thereof provided in the present disclosure are also characterized that a processing program, which is executed by an electronic device connected with the connection interface and a virtual network card, is able to read private key information, access a tabulation of remote shared data from the virtual network card, and display the tabulation on a graphic user interface.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: June 23, 2020
    Assignee: WALTON ADVANCED ENGINEERING INC.
    Inventors: Hong Chi Yu, Mao Ting Chang