Patents by Inventor Hong CHUANG
Hong CHUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150136364Abstract: A heat dissipation device includes a package carrier, heat dissipating fins, an atomizer and a driving unit. The package carrier has a carrying surface and a disposing surface divided into a first region and a second region. The heat dissipating fines are located in the second region and define an accommodating space with the package carrier. An extending direction of the heat dissipating fines is perpendicular to an extending direction of the package carrier. The atomizer is disposed on the heat dissipating fines and located in the accommodating space. The atomizer includes an atomization unit, a liquid containing cavity and a fluid channel. The liquid containing cavity, the heat dissipating fines and the package carrier define a fluid chamber. The driving unit is electrically connected to the atomizer so as to drive a working fluid to the atomization unit and atomize the working fluid into an atomization micro-mist.Type: ApplicationFiled: January 13, 2014Publication date: May 21, 2015Applicant: SUBTRON TECHNOLOGY CO., LTD.Inventor: Chih-Hong Chuang
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Patent number: 8707974Abstract: A wafer cleaning device comprising a wafer stage for holding a wafer having a surface to be washed, a first nozzle positioned above the wafer, a second nozzle positioned above the wafer. A first height is between the first nozzle and the surface and a second height is between the second nozzle and the surface, wherein the first height is shorter than the second height.Type: GrantFiled: December 11, 2009Date of Patent: April 29, 2014Assignee: United Microelectronics Corp.Inventors: Hsin-Ting Tsai, Cheng-Hung Yu, Chin-Kuang Liu, Ming-Hsin Lee, Wei-Hong Chuang, Kuei-Chang Tung, Yan-Yi Lu, Chin-Chin Wang
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Publication number: 20140096800Abstract: A wafer cleaning device comprising a wafer stage for holding a wafer having a surface to be washed, a first nozzle positioned above the wafer, a second nozzle positioned above the wafer. A first height is between the first nozzle and the surface and a second height is between the second nozzle and the surface, wherein the first height is shorter than the second height.Type: ApplicationFiled: December 17, 2013Publication date: April 10, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hsin-Ting Tsai, Cheng-Hung Yu, Chin-Kuang Liu, Ming-Hsin Lee, Wei-Hong Chuang, Kuei-Chang Tung, Yan-Yi Lu, Chin-Chin Wang
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Patent number: 8563363Abstract: A fabricating method of a semiconductor package structure is provided. A dielectric layer having a first surface and a second surface is provided. A patterned metal layer has been formed on the first surface of the dielectric layer. An opening going through the first and the second surfaces is formed. A carrier having a third surface and a fourth surface is formed at the second surface. A portion of the third surface is exposed by the opening of the dielectric layer. A semiconductor die having a joining surface and a side-surface is joined in the opening. At least a through hole going through the third and the fourth surfaces is formed. A metal layer having at least a heat conductive post extending from the fourth surface of the carrier to the through hole and disposed in the through hole and a containing cavity is formed on the fourth surface.Type: GrantFiled: August 21, 2012Date of Patent: October 22, 2013Assignee: Subtron Technology Co., Ltd.Inventors: Tzyy-Jang Tseng, Chin-Sheng Wang, Chih-Hong Chuang
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Patent number: 8552544Abstract: A package structure includes first and second substrates, a sealant and a filler. The first substrate has a surface including an active region and a bonding region. The first substrate has a component in the active region and a pad in bonding region. The pad is electrically connected to the component. The sealant is disposed on the surface surrounding the active region. The sealant has a breach at a side of the active region. The second substrate is bonded to the first substrate via the sealant. The second substrate has a first opening corresponding to the pad, and a second opening corresponding to the breach. The filler fills the second opening, covers the breach such that the first substrate, the second substrate, the sealant and the filler together form a sealed space for accommodating the component.Type: GrantFiled: August 2, 2010Date of Patent: October 8, 2013Assignee: Advanced Semiconductor Engineering, Inc.Inventor: Ching-Hong Chuang
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Patent number: 8510936Abstract: A manufacturing method of package carrier is provided. A first copper foil layer, a second copper foil layer on the first foil layer, a third copper foil layer and a fourth foil layer on the third foil layer are provided. The second copper foil layer is partially bonded the fourth copper foil layer by an adhesive gel so as to form a substrate of which the peripheral region is glued and the effective region is not glued. Therefore, the thinner substrate can be used in the following steps, such as patterning process or plating process. In addition, the substrate can be extended be the package carrier structure with odd-numbered layer or even-numbered layer.Type: GrantFiled: March 17, 2010Date of Patent: August 20, 2013Assignee: Subtron Technology Co., Ltd.Inventors: Chih-Hong Chuang, Tzu-Wei Huang
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Patent number: 8476003Abstract: An iterative rinse for fabrication of semiconductor devices is described. The iterative rinse includes a plurality of rinse cycles, wherein each of the plurality of rinse cycles has a different resistivity. The plurality of rinse cycles may include a first rinse of a semiconductor substrate with de-ionized (DI) water and carbon dioxide (CO2), followed by a second rinse the semiconductor substrate with DI water and CO2. The first rinse has a first resistivity; the second rinse has a second resistivity lower than the first resistivity.Type: GrantFiled: March 9, 2011Date of Patent: July 2, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Yao Lee, Wei-Hong Chuang, Li-Shiuan Chen, Ping-Hsi Yang
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Patent number: 8466920Abstract: A two dimensional (2D) vector graphics triangulation system and a method thereof are provided. The system includes a memory module and a triangle mesh processing module. The memory module temporarily stores a triangle mesh triangulated from a 2D vector graphics into a binary tree data structure. The triangle mesh processing module adjusts the triangle mesh, or re-performs a triangulation processing to a local region of the loop when a state of a loop of the 2D vector graphics is changed. The triangle mesh processing module includes a level of detail unit, which proportionally adjusts an error threshold according to a zoom condition of the loop, updates an error value of each boundary line when the loop is deformed, and splits a boundary line or merges two neighboring boundary lines according to the error values of the boundary lines and the error threshold.Type: GrantFiled: December 4, 2009Date of Patent: June 18, 2013Assignee: Institute for Information IndustryInventors: Huai-Che Lee, Jung-Hong Chuang, Tan-Chi Ho, Tsung-Sheng Fu, Yun Chien, Chia-Ming Liu
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Patent number: 8390013Abstract: A semiconductor package structure includes a dielectric layer, a patterned metal layer, a carrier, a metal layer and a semiconductor die. The dielectric layer has a first surface, a second surface and an opening. The patterned metal layer is disposed on the first surface. The carrier is disposed at the second surface and has a third surface, a fourth surface and at least a through hole. A portion of the third surface and the through hole are exposed by the opening. The metal layer is disposed on the fourth surface and has a containing cavity and at least a heat conductive post extending from the fourth surface and disposed in the through hole. An end of the heat conductive post protrudes away from the third surface, and the containing cavity is located on the end of the heat conductive post. The semiconductor die is located in the containing cavity.Type: GrantFiled: October 29, 2010Date of Patent: March 5, 2013Assignee: Subtron Technology Co., Ltd.Inventors: Tzyy-Jang Tseng, Chin-Sheng Wang, Chih-Hong Chuang
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Publication number: 20130011971Abstract: A fabricating method of a semiconductor package structure is provided. A dielectric layer having a first surface and a second surface is provided. A patterned metal layer has been formed on the first surface of the dielectric layer. An opening going through the first and the second surfaces is formed. A carrier having a third surface and a fourth surface is formed at the second surface. A portion of the third surface is exposed by the opening of the dielectric layer. A semiconductor die having a joining surface and a side-surface is joined in the opening. At least a through hole going through the third and the fourth surfaces is formed. A metal layer having at least a heat conductive post extending from the fourth surface of the carrier to the through hole and disposed in the through hole and a containing cavity is formed on the fourth surface.Type: ApplicationFiled: August 21, 2012Publication date: January 10, 2013Applicant: Subtron Technology Co., Ltd.Inventors: TZYY-JANG TSENG, Chin-Sheng Wang, Chih-Hong Chuang
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Publication number: 20120279630Abstract: A manufacturing method of a circuit substrate includes the following steps. The peripheries of two metal layers are bonded to form a sealed area. At least a through hole passing through the sealed area is formed. Two insulating layers are formed on the two metal layers. Two conductive layers are formed on the two insulating layers. The two insulating layers and the two conductive layers are laminated to the two metal layers bonded to each other, wherein the metal layers are embedded between the two insulating layers, and the two insulating layers fill into the through hole. The sealed area of the two metal layers is separated to form two separated circuit substrates. Therefore, the thinner substrate can be operated in the following steps, such as patterning process or plating process. In addition, the method may be extended to manufacture the circuit substrate with odd-numbered layer or even-numbered layer.Type: ApplicationFiled: July 19, 2012Publication date: November 8, 2012Applicant: SUBTRON TECHNOLOGY CO. LTD.Inventors: Chih-Hong Chuang, Tzu-Wei Huang
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Publication number: 20120231395Abstract: An iterative rinse for fabrication of semiconductor devices is described. The iterative rinse includes a plurality of rinse cycles, wherein each of the plurality of rinse cycles has a different resistivity. The plurality of rinse cycles may include a first rinse of a semiconductor substrate with de-ionized (DI) water and carbon dioxide (CO2), followed by a second rinse the semiconductor substrate with DI water and CO2. The first rinse has a first resistivity; the second rinse has a second resistivity lower than the first resistivity.Type: ApplicationFiled: March 9, 2011Publication date: September 13, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC")Inventors: Yung-Yao Lee, Wei-Hong Chuang, Li-Shiuan Chen, Ping-Hsi Yang
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Publication number: 20120181066Abstract: A package carrier is suitable for carrying a heat-generating element. The package carrier includes a substrate, an insulating structure with high thermal conductivity, and a patterned conductive layer. The substrate has a surface. The insulating structure with high thermal conductivity is configured on a portion of the surface of the substrate. The patterned conductive layer is configured on a portion of the surface of substrate, and a portion of the patterned conductive layer covers the insulating structure with high thermal conductivity. The heat-generating element is suitable for being configured on the portion of the patterned conductive layer which is located on the insulating structure with high thermal conductivity. A coefficient of thermal expansion (CTE) of the insulating structure with high thermal conductivity is between a CTE of the substrate and a CTE of the heat-generating element.Type: ApplicationFiled: March 1, 2011Publication date: July 19, 2012Applicant: SUBTRON TECHNOLOGY CO. LTD.Inventor: Chih-Hong Chuang
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Publication number: 20120088117Abstract: A substrate structure including a first metal substrate, a second metal substrate, a frame fixture, a first conductive layer, a second conductive layer, a first adhesive layer and a second adhesive layer is provided. The second metal substrate is stacked over the first metal substrate. The frame fixture is disposed around the first metal substrate and the second metal substrate. The first adhesive layer is disposed between the first conductive layer and the first metal substrate, and between the first conductive layer and the frame fixture. The first conductive layer is fixed on an upper surface of the frame fixture by the first adhesive layer. The second adhesive layer is disposed between the second conductive layer and the second metal substrate, and between the second conductive layer and the frame fixture. The second conductive layer is fixed on a lower surface of the frame fixture by the second adhesive layer.Type: ApplicationFiled: November 29, 2010Publication date: April 12, 2012Applicant: Subtron Technology Co., Ltd.Inventor: Chih-Hong Chuang
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Publication number: 20120058104Abstract: The present invention relates to use of a fermented soy extract as a prebiotic composition to protect beneficial bacteria in the gastrointestinal tract of an animal. Particularly, the fermented soy extract of the invention exhibits the prebiotic activity even under an antibiotic treatment. Also disclosed is combined use of an antibiotic and the fermented soy extract of the invention, which has advantages over administration of the antibiotic alone, such as decreasing the effective dose of the antibiotic and/or reducing side effects resulting from the antibiotic treatment.Type: ApplicationFiled: July 20, 2011Publication date: March 8, 2012Applicant: MICROBIO CO., LTD.Inventors: MING-HONG CHUANG, CHENG DER TONY YU, KUNG-MING LU
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Publication number: 20120025363Abstract: A package structure includes first and second substrates, a sealant and a filler. The first substrate has a surface including an active region and a bonding region. The first substrate has a component in the active region and a pad in bonding region. The pad is electrically connected to the component. The sealant is disposed on the surface surrounding the active region. The sealant has a breach at a side of the active region. The second substrate is bonded to the first substrate via the sealant. The second substrate has a first opening corresponding to the pad, and a second opening corresponding to the breach. The filler fills the second opening, covers the breach such that the first substrate, the second substrate, the sealant and the filler together form a sealed space for accommodating the component.Type: ApplicationFiled: August 2, 2010Publication date: February 2, 2012Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Ching-Hong Chuang
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Publication number: 20120007252Abstract: A semiconductor package structure includes a dielectric layer, a patterned metal layer, a carrier, a metal layer and a semiconductor die. The dielectric layer has a first surface, a second surface and an opening. The patterned metal layer is disposed on the first surface. The carrier is disposed at the second surface and has a third surface, a fourth surface and at least a through hole. A portion of the third surface and the through hole are exposed by the opening. The metal layer is disposed on the fourth surface and has a containing cavity and at least a heat conductive post extending from the fourth surface and disposed in the through hole. An end of the heat conductive post protrudes away from the third surface, and the containing cavity is located on the end of the heat conductive post. The semiconductor die is located in the containing cavity.Type: ApplicationFiled: October 29, 2010Publication date: January 12, 2012Applicant: Subtron Technology Co. Ltd.Inventors: TZYY-JANG TSENG, Chin-Sheng Wang, Chih-Hong Chuang
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Publication number: 20110154657Abstract: A manufacturing method of package carrier is provided. A first copper foil layer, a second copper foil layer on the first foil layer, a third copper foil layer and a fourth foil layer on the third foil layer are provided. The second copper foil layer is partially bonded the fourth copper foil layer by an adhesive gel so as to form a substrate of which the peripheral region is glued and the effective region is not glued. Therefore, the thinner substrate can be used in the following steps, such as patterning process or plating process. In addition, the substrate can be extended be the package carrier structure with odd-numbered layer or even-numbered layer.Type: ApplicationFiled: March 17, 2010Publication date: June 30, 2011Applicant: SUBTRON TECHNOLOGY CO. LTD.Inventors: Chih-Hong Chuang, Tzu-Wei Huang
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Publication number: 20110154658Abstract: A manufacturing method of a circuit substrate includes the following steps. The peripheries of two metal layers are bonded to form a sealed area. At least a through hole passing through the sealed area is formed. Two insulating layers are formed on the two metal layers. Two conductive layers are formed on the two insulating layers. The two insulating layers and the two conductive layers are laminated to the two metal layers bonded to each other, wherein the metal layers are embedded between the two insulating layers, and the two insulating layers fill into the through hole. The sealed area of the two metal layers is separated to form two separated circuit substrates. Therefore, the thinner substrate can be operated in the following steps, such as patterning process or plating process. In addition, the method may be extended to manufacture the circuit substrate with odd-numbered layer or even-numbered layer.Type: ApplicationFiled: December 28, 2010Publication date: June 30, 2011Applicant: SUBTRON TECHNOLOGY CO. LTD.Inventors: Chih-Hong Chuang, Tzu-Wei Huang
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Publication number: 20110153902Abstract: A test interface card includes: a first specification bus adapted for coupling between a first specification interface controller of a device under test (DUT) and a signal converting interface card, and for transmitting a first test signal that is outputted by the first specification interface controller to the signal converting interface card for processing; a second specification bus adapted for coupling between the signal converting interface card and a storage module of the DUT, and for transmitting a processed signal that is outputted by the signal converting interface card as a result of processing the first test signal to the storage module; and a third specification bus adapted for forming a closed circuit with a second specification interface controller of the DUT, and for transmitting a second test signal that is outputted by the second specification interface controller back to the second specification interface controller.Type: ApplicationFiled: September 16, 2010Publication date: June 23, 2011Applicant: Wistron CorporationInventors: Chiao-Lun Tsai, Kuo-Hong Chuang