Patents by Inventor Hong-Dyi Chang
Hong-Dyi Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11515239Abstract: A quad flat no-lead (QFN) package structure including a lead frame, a semiconductor die, and an encapsulating material. The lead frame includes a die pad and a plurality of contacts surrounding the die pad. The semiconductor die is disposed on the die pad and electrically connected to the plurality of contacts, wherein a shortest distance between the semiconductor die and a first side of the die pad is shorter than a shortest distance between the semiconductor die to a second side of the die pad, and the first side is opposite to the second side. The encapsulating material encapsulates the lead frame and the semiconductor die and partially exposing the plurality of contacts, wherein an aspect ratio of the QFN package is substantially equal to or greater than 3.Type: GrantFiled: February 8, 2021Date of Patent: November 29, 2022Assignee: Novatek Microelectronics Corp.Inventors: Hong-Dyi Chang, Tai-Hung Lin, Jhih-Siou Cheng
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Patent number: 11244891Abstract: An integrated circuit package, a die carrier, and a die are provided. The die carrier includes at least one die pad and a plurality of leads. The at least one die pad is suitable for carrying the die. The leads surround the at least one die pad. The leads are disposed on four sides of the die carrier. A length of a long side among the four sides is twice or more a length of a short side among the four sides. The die carrier is suitable for a QFN package or a QFP package.Type: GrantFiled: July 21, 2020Date of Patent: February 8, 2022Assignee: NOVATEK MICROELECTRONICS CORP.Inventors: Jhih-Siou Cheng, Hong-Dyi Chang, Chun-Wei Kang, Chun-Fu Lin, Ju-Lin Huang
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Publication number: 20220028775Abstract: An integrated circuit package, a die carrier, and a die are provided. The die carrier includes at least one die pad and a plurality of leads. The at least one die pad is suitable for carrying the die. The leads surround the at least one die pad. The leads are disposed on four sides of the die carrier. A length of a long side among the four sides is twice or more a length of a short side among the four sides. The die carrier is suitable for a QFN package or a QFP package.Type: ApplicationFiled: July 21, 2020Publication date: January 27, 2022Applicant: Novatek Microelectronics Corp.Inventors: Jhih-Siou Cheng, Hong-Dyi Chang, Chun-Wei Kang, Chun-Fu Lin, Ju-Lin Huang
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Publication number: 20220020673Abstract: A quad flat no-lead (QFN) package structure including a lead frame, a semiconductor die, and an encapsulating material. The lead frame includes a die pad and a plurality of contacts surrounding the die pad. The semiconductor die is disposed on the die pad and electrically connected to the plurality of contacts, wherein a shortest distance between the semiconductor die and a first side of the die pad is shorter than a shortest distance between the semiconductor die to a second side of the die pad, and the first side is opposite to the second side. The encapsulating material encapsulates the lead frame and the semiconductor die and partially exposing the plurality of contacts, wherein an aspect ratio of the QFN package is substantially equal to or greater than 3.Type: ApplicationFiled: February 8, 2021Publication date: January 20, 2022Applicant: Novatek Microelectronics Corp.Inventors: Hong-Dyi Chang, Tai-Hung Lin, Jhih-Siou Cheng
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Patent number: 8970015Abstract: Various semiconductor devices are disclosed. An exemplary device includes: a substrate; a gate structure disposed over the substrate, wherein the gate structure includes a source region and a drain region; a first etch stop layer disposed over the gate structure, a second etch stop layer disposed over the source region and the drain region; a dielectric layer disposed over the substrate; and a gate contact, a source contact, and a drain contact. The dielectric layer is disposed over both etch stop layers. The gate contact extends through the dielectric layer and the first etch stop layer to the gate structure. The source contact and the drain contact extend through the dielectric layer and the second etch stop layer respectively to the source region and the drain region.Type: GrantFiled: December 20, 2013Date of Patent: March 3, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Dyi Chang, Pei-Chao Su, Kong-Beng Thei, Hun-Jan Tao, Harry-Hak-Lay Chuang
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Publication number: 20140103407Abstract: Various semiconductor devices are disclosed. An exemplary device includes: a substrate; a gate structure disposed over the substrate, wherein the gate structure includes a source region and a drain region; a first etch stop layer disposed over the gate structure, a second etch stop layer disposed over the source region and the drain region; a dielectric layer disposed over the substrate; and a gate contact, a source contact, and a drain contact. The dielectric layer is disposed over both etch stop layers. The gate contact extends through the dielectric layer and the first etch stop layer to the gate structure. The source contact and the drain contact extend through the dielectric layer and the second etch stop layer respectively to the source region and the drain region.Type: ApplicationFiled: December 20, 2013Publication date: April 17, 2014Inventors: Hong-Dyi CHANG, Pei-Chao Su, Kong-Beng Thei, Hun-Jan Tao, Harry-Hak-Lay Chuang
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Patent number: 8648446Abstract: Various semiconductor devices are disclosed. An exemplary device includes: a substrate; a gate structure disposed over the substrate, wherein the gate structure includes a source region and a drain region; a first etch stop layer disposed over the gate structure, a second etch stop layer disposed over the source region and the drain region; a dielectric layer disposed over the substrate; and a gate contact, a source contact, and a drain contact. The dielectric layer is disposed over both etch stop layers. The gate contact extends through the dielectric layer and the first etch stop layer to the gate structure. The source contact and the drain contact extend through the dielectric layer and the second etch stop layer respectively to the source region and the drain region.Type: GrantFiled: July 17, 2013Date of Patent: February 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Dyi Chang, Pei-Chao Su, Kong-Beng Thei, Hun-Jan Tao, Harry Hak-Lay Chuang
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Publication number: 20130299921Abstract: Various semiconductor devices are disclosed. An exemplary device includes: a substrate; a gate structure disposed over the substrate, wherein the gate structure includes a source region and a drain region; a first etch stop layer disposed over the gate structure, a second etch stop layer disposed over the source region and the drain region; a dielectric layer disposed over the substrate; and a gate contact, a source contact, and a drain contact. The dielectric layer is disposed over both etch stop layers. The gate contact extends through the dielectric layer and the first etch stop layer to the gate structure. The source contact and the drain contact extend through the dielectric layer and the second etch stop layer respectively to the source region and the drain region.Type: ApplicationFiled: July 17, 2013Publication date: November 14, 2013Inventors: Hong-Dyi Chang, Pei-Chao Su, Kong-Beng Thei, Hun-Jan Tao, Harry Hak-Lay Chuang
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Patent number: 8530326Abstract: A method of semiconductor device fabrication including forming a plurality of gate structures in a first portion of a substrate, wherein the plurality of gate structures have a first height. A first metal gate structure is formed in a second portion of the substrate, the first metal gate structure being surrounded by an isolation region. A plurality of dummy gate structures is formed in the second portion of the substrate. The plurality of dummy gate structures are configured in a ring formation encircling the metal gate structure and the isolation region. The plurality of dummy structures have a top surface that is substantially planar with the plurality of gate structures and covers at least 5% of a pattern density of the second portion of the substrate.Type: GrantFiled: June 29, 2012Date of Patent: September 10, 2013Inventors: Su-Chen Lai, Ming-Yuan Wu, Kong-Beng Thei, Hak-Lay Chuang, Chiung-Han Yeh, Hong-Dyi Chang, Kuo Cheng-Cheng, Chien-Hung Wu, Tzung-Chi Lee
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Patent number: 8497169Abstract: Various methods for protecting a gate structure during contact formation are disclosed. An exemplary method includes: forming a gate structure over a substrate, wherein the gate structure includes a gate and the gate structure interposes a source region and a drain region disposed in the substrate; patterning a first etch stop layer such that the first etch stop layer is disposed on the source region and the drain region; patterning a second etch stop layer such that the second etch stop layer is disposed on the gate structure; and forming a source contact, a drain contact, and a gate contact, wherein the source contact and the drain contact extend through the first etch stop layer and the gate contact extends through the second etch stop layer, wherein the forming the source contact, the drain contact, and the gate contact includes simultaneously removing the first etch stop layer and the second etch stop layer to expose the gate, source region, and drain region.Type: GrantFiled: May 18, 2012Date of Patent: July 30, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Dyi Chang, Pei-Chao Su, Kong-Beng Thei, Hun-Jan Tao, Harry Hak-Lay Chuang
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Publication number: 20130049192Abstract: A semiconductor package for a stacked chip includes a first semiconductor chip, comprising a metal layer; a through-silicon-via, penetrating a top surface of the first semiconductor chip and electrically connected to the metal layer; a redistribution layer, formed on the top surface of the first semiconductor chip, and electrically connected to the through-silicon-via; and a second semiconductor chip, disposed on the first semiconductor chip and electrically connected to the first semiconductor chip via the redistribution layer.Type: ApplicationFiled: August 22, 2012Publication date: February 28, 2013Inventors: Hong-Dyi Chang, Tai-Hung Lin
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Publication number: 20120270379Abstract: A method of semiconductor device fabrication including forming a plurality of gate structures in a first portion of a substrate, wherein the plurality of gate structures have a first height. A first metal gate structure is formed in a second portion of the substrate, the first metal gate structure being surrounded by an isolation region. A plurality of dummy gate structures is formed in the second portion of the substrate. The plurality of dummy gate structures are configured in a ring formation encircling the metal gate structure and the isolation region. The plurality of dummy structures have a top surface that is substantially planar with the plurality of gate structures and covers at least 5% of a pattern density of the second portion of the substrate.Type: ApplicationFiled: June 29, 2012Publication date: October 25, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC")Inventors: Su-Chen Lai, Ming-Yuan Wu, Kong-Beng Thei, Harry Hak-Lay Chuang, Chiung-Han Yeh, Hong-Dyi Chang, Kuo Cheng Cheng, Chien-Hung Wu, Tzung-Chi Lee
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Publication number: 20120228679Abstract: Various methods for protecting a gate structure during contact formation are disclosed. An exemplary method includes: forming a gate structure over a substrate, wherein the gate structure includes a gate and the gate structure interposes a source region and a drain region disposed in the substrate; patterning a first etch stop layer such that the first etch stop layer is disposed on the source region and the drain region; patterning a second etch stop layer such that the second etch stop layer is disposed on the gate structure; and forming a source contact, a drain contact, and a gate contact, wherein the source contact and the drain contact extend through the first etch stop layer and the gate contact extends through the second etch stop layer, wherein the forming the source contact, the drain contact, and the gate contact includes simultaneously removing the first etch stop layer and the second etch stop layer to expose the gate, source region, and drain region.Type: ApplicationFiled: May 18, 2012Publication date: September 13, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hong-Dyi Chang, Pei-Chao Su, Kong-Beng Thei, Hun-Jan Tao, Harry Hak-Lay Chuang
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Patent number: 8237227Abstract: A semiconductor device is provided which includes a semiconductor substrate having a first portion and a second portion, transistors formed in the first portion of the substrate, each transistor having a gate structure with a high-k dielectric and a metal gate, a device element formed in the second portion of the substrate, the device element being isolated by an isolation region, and a polishing stopper formed adjacent the isolation region and having a surface that is substantially planar with a surface of the gate structures of the transistors in the first region.Type: GrantFiled: June 3, 2009Date of Patent: August 7, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Chen Lai, Ming-Yuan Wu, Kong-Beng Thei, Harry Hak-Lay Chuang, Chiung-Han Yeh, Hong-Dyi Chang, Kuo Cheng Cheng, Chien-Hung Wu, Tzung-Chi Lee
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Patent number: 8202776Abstract: A method for fabricating a semiconductor device is disclosed. The method includes providing a substrate; forming at least one gate structure over the substrate; forming a plurality of doped regions in the substrate; forming an etch stop layer over the substrate; removing a first portion of the etch stop layer, wherein a second portion of the etch stop layer remains over the plurality of doped regions; forming a hard mask layer over the substrate; removing a first portion of the hard mask layer, wherein a second portion of the hard mask layer remains over the at least one gate structure; and forming a first contact through the second portion of the hard mask layer to the at least one gate structure, and a second contact through the second portion of the etch stop layer to the plurality of doped regions.Type: GrantFiled: April 22, 2009Date of Patent: June 19, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Dyi Chang, Pei-Chao Su, Kong-Beng Thei, Hun-Jan Tao, Harry Hak-Lay Chuang
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Publication number: 20100270627Abstract: A method for fabricating a semiconductor device is disclosed. The method includes providing a substrate; forming at least one gate structure over the substrate; forming a plurality of doped regions in the substrate; forming an etch stop layer over the substrate; removing a first portion of the etch stop layer, wherein a second portion of the etch stop layer remains over the plurality of doped regions; forming a hard mask layer over the substrate; removing a first portion of the hard mask layer, wherein a second portion of the hard mask layer remains over the at least one gate structure; and forming a first contact through the second portion of the hard mask layer to the at least one gate structure, and a second contact through the second portion of the etch stop layer to the plurality of doped regions.Type: ApplicationFiled: April 22, 2009Publication date: October 28, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hong-Dyi Chang, Pei-Chao Su, Kong-Beng Thei, Hun-Jan Tao, Harry Hak-Lay Chuang
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Publication number: 20100052060Abstract: A semiconductor device is provided which includes a semiconductor substrate having a first portion and a second portion, transistors formed in the first portion of the substrate, each transistor having a gate structure with a high-k dielectric and a metal gate, a device element formed in the second portion of the substrate, the device element being isolated by an isolation region, and a polishing stopper formed adjacent the isolation region and having a surface that is substantially planar with a surface of the gate structures of the transistors in the first region.Type: ApplicationFiled: June 3, 2009Publication date: March 4, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Su-Chen Lai, Ming-Yuan Wu, Kong-Beng Thei, Harry Hak-Lay Chuang, Chiung-Han Yeh, Hong-Dyi Chang, Kuo Cheng Cheng, Chien-Hung Wu, Tzung-Chi Lee