Patents by Inventor Hong Gao
Hong Gao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12283586Abstract: An integrated circuit (IC) device includes a circuit region, a lower metal layer over the circuit region, and an upper metal layer over the lower metal layer. The lower metal layer includes a plurality of lower conductive patterns elongated along a first axis. The upper metal layer includes a plurality of upper conductive patterns elongated along a second axis transverse to the first axis. The plurality of upper conductive patterns includes at least one input or output configured to electrically couple the circuit region to external circuitry outside the circuit region. The upper metal layer further includes a first lateral upper conductive pattern contiguous with and projecting, along the first axis, from a first upper conductive pattern among the plurality of upper conductive patterns. The first lateral upper conductive pattern is over and electrically coupled to a first lower conductive pattern among the plurality of lower conductive patterns.Type: GrantFiled: August 31, 2021Date of Patent: April 22, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Ling Chang, Chih-Liang Chen, Hui-Zhong Zhuang, Chia-Tien Wu, Jia-Hong Gao
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Publication number: 20250121143Abstract: An atomizer includes an atomization assembly and a medicine storage assembly idetachably coupled to the atomization assembly, wherein the medicine storage assembly includes a storage housing, and a medicine liquid transporting cotton disposed in the storage housing, wherein the atomization assembly includes a fixing housing and an atomizing element disposed in the fixing housing to align with the medicine liquid transporting cotton in a manner that the medicine liquid transporting element is arranged to deliver medicine liquid to the atomizing element.Type: ApplicationFiled: December 2, 2024Publication date: April 17, 2025Inventors: Qi DING, Xueqing ZU, Chunxiao HU, Bo WU, Xiaoshan LI, Hong GAO
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Publication number: 20250111771Abstract: A method for mining an alarm causality, a device for mining an alarm causality, and a storage medium. The method for mining the alarm causality includes: building a system alarm environment (101) for deep reinforcement learning based on system alarm information and root cause label data of the system alarm information; and learning and generating an alarm causality model (102) representing the alarm causality and structure through an interaction between a deep reinforcement learning agent and the system alarm environment.Type: ApplicationFiled: June 14, 2022Publication date: April 3, 2025Inventors: Qingpeng NONG, Zhongliang LI, Xiangsheng ZHOU, Hong GAO, Yaofeng TU
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Patent number: 12253974Abstract: Provided are a metadata processing method and apparatus, and a computer-readable storage medium. In the metadata processing method, a management server obtains metadata to be processed, wherein the metadata to be processed includes a directory structure and file attributes; and according to a load condition of at least one first node for storing the file attributes and based on a rule that file attributes of a same directory are stored in a same first node, the management server stores, in the at least one first node, the file attributes of directories in the directory structure in a distributed manner.Type: GrantFiled: June 24, 2020Date of Patent: March 18, 2025Assignee: ZTE CORPORATIONInventors: Yinjun Han, Bo Wang, Yaofeng Tu, Hong Gao
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Patent number: 12218670Abstract: An integrated circuit includes a first clocked forwarding-switch and a second clocked forwarding-switch each implemented with strong transistors in at least one strong active-region structure. The integrated circuit also includes a first clocked inverter and a second clocked inverter each implemented with weak transistors in at least one weak active-region structure. The integrated circuit further includes a first inverter cross coupled with the first clocked inverter and a second inverter cross coupled with the second clocked inverter. An output of the first clocked forwarding-switch is conductively connected with an output of the first clocked inverter, and an output of the second clocked forwarding-switch is conductively connected with an output of the second clocked inverter.Type: GrantFiled: June 12, 2023Date of Patent: February 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: I-Wen Wang, Po-Chih Cheng, Jia-Hong Gao, Kuang-Ching Chang, Tzu-Ying Lin, Jerry Chang Jui Kao
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Patent number: 12217829Abstract: The technology disclosed relates to determining pathogenicity of variants. In particular, the technology disclosed relates to generating amino acid-wise distance channels for a plurality of amino acids in a protein. Each of the amino acid-wise distance channels has voxel-wise distance values for voxels in a plurality of voxels. A tensor includes the amino acid-wise distance channels and at least an alternative allele of the protein expressed by a variant. A deep convolutional neural network determines a pathogenicity of the variant based at least in part on processing the tensor. The technology disclosed further augments the tensor with supplemental information like a reference allele of the protein, evolutionary conservation data about the protein, annotation data about the protein, and structure confidence data about the protein.Type: GrantFiled: April 15, 2021Date of Patent: February 4, 2025Assignee: Illumina, Inc.Inventors: Tobias Hamp, Hong Gao, Kai-How Farh
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Publication number: 20250036846Abstract: A method of manufacturing an integrated circuit (IC) includes forming a first active region in a first cell. The method further includes forming a plurality of second active regions in a second cell, wherein the second cell abuts the first cell, and a height of the second cell is different from a height of the first cell. The method further includes forming a plurality of gate structures extending across each of the first active region and the plurality of second active regions. The method further includes removing a first portion of a first gate structure of the plurality of gate structures at an interface between the first cell and the second cell, wherein the first portion of the first gate structure is between the first active region and the plurality of second active regions.Type: ApplicationFiled: October 17, 2024Publication date: January 30, 2025Inventors: Jia-Hong GAO, Hui-Zhong ZHUANG
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Publication number: 20240413812Abstract: An integrated circuit includes a first clocked forwarding-switch and a second clocked forwarding-switch each implemented with strong transistors in at least one strong active-region structure. The integrated circuit also includes a first clocked inverter and a second clocked inverter each implemented with weak transistors in at least one weak active-region structure. The integrated circuit further includes a first inverter cross coupled with the first clocked inverter and a second inverter cross coupled with the second clocked inverter. An output of the first clocked forwarding-switch is conductively connected with an output of the first clocked inverter, and an output of the second clocked forwarding-switch is conductively connected with an output of the second clocked inverter.Type: ApplicationFiled: June 12, 2023Publication date: December 12, 2024Inventors: I-Wen WANG, Po-Chih CHENG, Jia-Hong GAO, Kuang-Ching CHANG, Tzu-Ying LIN, Jerry Chang Jui KAO
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Publication number: 20240387505Abstract: A method of manufacturing an integrated circuit (IC) device includes forming, in a circuit region, active regions elongated along a first axis, and gate regions over the active regions and elongated along a second axis. The method further includes depositing a lower metal layer over the circuit region, patterning the lower metal layer to form lower conductive patterns elongated along the first axis, depositing an upper metal layer over the lower metal layer, and patterning the upper metal layer to form upper conductive patterns elongated along the second axis and first lateral upper conductive pattern. The upper conductive patterns include at least one input or output configured to electrically couple the circuit region to external circuitry. The first lateral upper conductive pattern is contiguous with and projects, along the first axis, from a first upper conductive pattern, and is over and electrically coupled to a first lower conductive pattern.Type: ApplicationFiled: July 31, 2024Publication date: November 21, 2024Inventors: Wei-Ling CHANG, Chih-Liang CHEN, Hui-Zhong ZHUANG, Chia-Tien WU, Jia-Hong GAO
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Patent number: 12146138Abstract: A method of treating an inflammatory disorder in a subject, comprising administering to a subject in need thereof a nucleic acid molecule for inhibiting the expression of Hom-1.Type: GrantFiled: February 18, 2022Date of Patent: November 19, 2024Inventors: Zhenglun Zhu, Hong Gao
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Publication number: 20240364667Abstract: Disclosed are a data sharing method, a network side device, a system, an electronic device, and a storage medium. The method includes: creating a sandbox for a data provider, and synchronizing information on the sandbox to a second network side device, wherein the sandbox is bound to an original database, and the information on the sandbox includes metadata of the original database; receiving a sandbox access request initiated by a data application party and forwarded by the second network side device, wherein the sandbox access request carries metadata of request data; collecting, in the original database bound to the sandbox, original data queried on the basis of the metadata of the request data; and generating response data to the sandbox access request according to the collected original data, and notifying, by means of the second network side device, the data application party to acquire the response data from the sandbox.Type: ApplicationFiled: June 14, 2022Publication date: October 31, 2024Inventors: Ming ZENG, Dezheng WANG, Haisheng GUO, Yaofeng TU, Hong GAO
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Patent number: 12124785Abstract: A method of manufacturing an integrated circuit (IC) includes forming a first active region in a first cell. The method includes forming a plurality of second active regions in a second cell, wherein the second cell abuts the first cell. The method includes forming a third active region in a third cell, wherein the second cell is between the first cell and the third cell, and a height of the second cell is different from a height of the first cell or the third cell. The method includes forming a plurality of gate structures extending across each of the first active region, the plurality of second active regions, and the third active region. The method includes removing a first portion of a first gate structure at an interface between the first cell and the second cell between the first active region and the plurality of second active regions.Type: GrantFiled: August 10, 2023Date of Patent: October 22, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jia-Hong Gao, Hui-Zhong Zhuang
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Publication number: 20240299675Abstract: An atomizer includes a medicament feeding unit, a medicament delivering vessel, and an atomizing unit, the medicament delivering vessel includes a medicament guiding tube communicated to the medicament feeding unit, and an elastic membrane bladder wound around the medicament guiding tube, wherein when medicament liquid is fed into the medicament delivering vessel through the medicament feeding unit, the elastic membrane bladder is inflated and is capable of generating an elastic driving force for driving the medicament liquid to be fed towards the atomizing unit for atomizing the medicament liquid. A depressurization receptacle has a curved medicament delivery passage is also provided for causing pressure loss of the medicament liquid.Type: ApplicationFiled: March 4, 2024Publication date: September 12, 2024Inventors: Qi DING, Chunxiao HU, Bo WU, Xiaoshan LI, Hong GAO
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Patent number: 12089321Abstract: An induction cooker includes a rectifying device, a first energy-storage device, a switch device, a second energy-storage device, a heating device and a control device. The capacitance of the second energy-storage device is greater than the capacitance of the first energy-storage device. When the induction cooker is just starting, the control device controls the switch device to be turned off, such that the heating device generates an output current according to an energy of the first energy-storage device. The control device determines whether a pot is on the heating device according to a change state of the output current. When the pot is on the heating device, the control device controls the switch device to be turned on, such that the first and second energy-storage devices are coupled, and the heating device heats the pot according to energies of the first and second energy-storage devices.Type: GrantFiled: May 15, 2020Date of Patent: September 10, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Yu-Min Meng, Jhih-Hong Gao, Chun-wei Lin, Yu-Tsung Lee, Chun Chang
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Publication number: 20240297063Abstract: Electrostatic chucks and methods of forming electrostatic chucks are disclosed. Exemplary electrostatic chucks include a ceramic body, a device embedded within the ceramic body, and an interface layer formed overlying the device. Exemplary methods include providing ceramic precursor material within a mold, providing a device, coating the device with an interface material to form a coated device, placing the coated device on or within the ceramic precursor material, and sintering the ceramic precursor material to form the electrostatic chuck and an interface layer between the device and ceramic material formed during the step of sintering.Type: ApplicationFiled: May 13, 2024Publication date: September 5, 2024Inventors: Joaquin Aguilar Santillan, Hong Gao, Shanker Kuttath
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Patent number: 12073163Abstract: An integrated circuit (IC) includes a first, second and third semiconductor cell regions. The first cell region includes a first active region having a first dopant type. The second semiconductor cell region abuts the first cell region in a second direction, and includes second and third active regions having correspondingly a second dopant type and the first dopant type. The second active region is between the first and third active regions. The third cell region abuts the second cell region in the second direction, and includes a fourth active region having the second dopant type. The third active region is between the fourth active region and the second active region. The second semiconductor cell region has a height 2H, and the first, second and third semiconductor cell regions collectively have a height 3H.Type: GrantFiled: August 18, 2021Date of Patent: August 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jia-Hong Gao, Hui-Zhong Zhuang
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Publication number: 20240274592Abstract: A cell region of a semiconductor device includes: active regions (ARs) formed as predetermined shapes on a substrate including first and second ARs having a first shape and correspondingly first and second dopant types, a third AR having a second shape and the second dopant type, and a fourth AR having a third shape and the first dopant type. The first and second ARs are arranged in a first area of the cell region. The third and fourth ARs are arranged in a second area of the cell region. The second area is adjacent to the first area relative to a first direction (e.g., Y-axis (vertical adjacency-architecture) or X-axis (horizontal adjacency-architecture)). The first shape is smaller than the second shape. The second shape is smaller than the third shape.Type: ApplicationFiled: June 12, 2023Publication date: August 15, 2024Inventors: Han-Chung CHANG, Kuang-Ching CHANG, Jia-Hong GAO, Po-Chih CHENG, Hui-Zhong ZHUANG
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Patent number: 12062565Abstract: Electrostatic chucks and methods of using electrostatic chucks are disclosed. Exemplary electrostatic chucks include a ceramic body, a heating element embedded within the ceramic body, and two or more temperature measurement devices embedded within the ceramic body. Exemplary methods include measuring temperatures within the electrostatic chuck using two or more vertically spaced-apart temperature measurement devices.Type: GrantFiled: June 24, 2022Date of Patent: August 13, 2024Assignee: ASM IP Holding B.V.Inventors: Joaquin Aguilar Santillan, Hong Gao, Shanker Kuttath, ChangMin Lee
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Publication number: 20240250671Abstract: An integrated circuit (IC) device includes a master latch circuit having a data output, a slave latch circuit having a data input electrically coupled to the data output of the master latch circuit, and a clock circuit electrically coupled to the master latch circuit and the slave latch circuit. The slave latch circuit is physically between the master latch circuit and at least a part of the clock circuit.Type: ApplicationFiled: April 2, 2024Publication date: July 25, 2024Inventors: Cheng-Yu LIN, Yung-Chen CHIEN, Jia-Hong GAO, Jerry Chang Jui KAO, Hui-Zhong ZHUANG
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Patent number: 11996312Abstract: Electrostatic chucks and methods of forming electrostatic chucks are disclosed. Exemplary electrostatic chucks include a ceramic body, a device embedded within the ceramic body, and an interface layer formed overlying the device. Exemplary methods include providing ceramic precursor material within a mold, providing a device, coating the device with an interface material to form a coated device, placing the coated device on or within the ceramic precursor material, and sintering the ceramic precursor material to form the electrostatic chuck and an interface layer between the device and ceramic material formed during the step of sintering.Type: GrantFiled: January 6, 2022Date of Patent: May 28, 2024Assignee: ASM IP Holding B.V.Inventors: Joaquin Aguilar Santillan, Hong Gao, Shanker Kuttath