Patents by Inventor Hong-guang SHI

Hong-guang SHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • IEEE1588 protocol negative testing method
    Patent number: 8775885
    Abstract: The present invention relates to an IEEE1588 protocol negative testing method, comprises steps of: connecting a IEEE1588 tester and a slave clock DUT to establish a real-time closed-loop feedback mechanism; taking the IEEE1588 tester as a master clock, and establishing a stable time synchronization with the slave clock DUT; obtaining the timing offset or path delay of the slave clock DUT before disturbance; assembling an abnormal message in a frame and sending it to the slave clock DUT; calculating the timing offset or path delay increment after disturbance of the abnormal message; determining whether there is a sudden change in the timing offset or path delay of the slave clock DUT, wherein if there is no sudden change, the test passes; otherwise the test fails.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: July 8, 2014
    Assignees: Xu Ji Group Corporation, State Grid Corporation of China
    Inventors: Xiao-hui Song, Yong Wei, Fu-sheng Li, Quan-sheng Cui, Jun-feng Di, Jun-gang Li, Yun-zhao Zheng, Hong-guang Shi, Tuo-fu Zheng, Yi-ding Song, Bao-shan Zhang
  • IEEE1588 PROTOCOL NEGATIVE TESTING METHOD
    Publication number: 20130103997
    Abstract: The present invention relates to an IEEE1588 protocol negative testing method, comprises steps of: connecting a IEEE1588 tester and a slave clock DUT to establish a real-time closed-loop feedback mechanism; taking the IEEE1588 tester as a master clock, and establishing a stable time synchronization with the slave clock DUT; obtaining the timing offset or path delay of the slave clock DUT before disturbance; assembling an abnormal message in a frame and sending it to the slave clock DUT; calculating the timing offset or path delay increment after disturbance of the abnormal message; determining whether there is a sudden change in the timing offset or path delay of the slave clock DUT, wherein if there is no sudden change, the test passes; otherwise the test fails.
    Type: Application
    Filed: August 28, 2012
    Publication date: April 25, 2013
    Applicants: STATE GRID CORPORATION OF CHINA, XU JI GROUP CORPORATION
    Inventors: Xiao-hui SONG, Yong WEI, Fu-sheng LI, Quan-sheng CUI, Jun-feng DI, Jun-gang LI, Yun-zhao ZHENG, Hong-guang SHI, Tuo-fu ZHENG, Yi-ding SONG, Bao-shan ZHANG