Abstract: A parameterizable design system is for use with semiconductor analog circuits and includes an interface unit connected to provide access to the system, a database unit connected to supply a library of parameterizable analog building blocks for a design entity, and a parameterization unit connected to select a parameter for one of the library of parameterizable analog building blocks to meet a design specification of the design entity. Additionally, the parameterizable design system may also include a simulation unit connected to simulate an operation of the design entity employing the parameter, and an analyzer unit connected to analyze a sensitivity of the parameter for the design entity based on the design specification. A method of designing a semiconductor analog circuit is also included.

Abstract: A parameterizable design system is for use with semiconductor analog circuits and includes an interface unit connected to provide access to the system, a database unit connected to supply a library of parameterizable analog building blocks for a design entity, and a parameterization unit connected to select a parameter for one of the library of parameterizable analog building blocks to meet a design specification of the design entity. Additionally, the parameterizable design system may also include a simulation unit connected to simulate an operation of the design entity employing the parameter, and an analyzer unit connected to analyze a sensitivity of the parameter for the design entity based on the design specification. A method of designing a semiconductor analog circuit is also included.

Abstract: An on-chip capacitive device comprises a semiconductor substrate, a MOS capacitor formed on the semiconductor substrate, and a metal interconnect capacitor formed at least in part in a region above the MOS capacitor. The MOS capacitor and the metal interconnect capacitor are connected in parallel to form a single capacitive device. The capacitance densities of the MOS capacitor and the metal interconnect capacitor are, thereby, combined. Advantageously, significant capacitance density gains can be achieved without additional processing steps.

Abstract: An on-chip capacitive device comprises a semiconductor substrate, a MOS capacitor formed on the semiconductor substrate, and a metal interconnect capacitor formed at least in part in a region above the MOS capacitor. The MOS capacitor and the metal interconnect capacitor are connected in parallel to form a single capacitive device. The capacitance densities of the MOS capacitor and the metal interconnect capacitor are, thereby, combined. Advantageously, significant capacitance density gains can be achieved without additional processing steps.

Abstract: A semiconductor device, and a process for fabricating the device, is disclosed. The semiconductor device is an MOS device in which the gate is bounded by spacers, which are in turn bounded by a trench in a trench dielectric layer formed on a semiconductor substrate. The device is formed by lithographically defining a sacrificial gate on the surface of the semiconductor substrate. The trench dielectric layer is then formed on the semiconductor substrate and adjacent to the sacrificial gate. The trench dielectric layer is planarized and, subsequent to planarization, the sacrificial gate is no longer covered by the trench dielectric layer. The sacrificial gate is then removed, which leaves a trench in the trench dielectric layer. Dielectric spacers are then formed in the trench. The distance between the spacers defines the gate length of the semiconductor device. After the spacers are formed, the device gate is formed. At least a portion of the gate is formed in the trench.

Abstract: A method of fabricating an IC comprises the steps of: (a) forming trench isolation regions in a surface of a semiconductor body; and (b) forming a tub-tie region between at least one pair of the trench isolation regions (when viewed in cross-section) by a process that includes the following steps: (b1) forming a first photolithographic mask that covers and is in registration with the tub-tie region; (b2) implanting ions of a first conductivity-type to form a tub region adjacent the tub-tie region; (b3) removing the first mask; (b4) forming a second photolithographic mask that has an opening that exposes most of the underlying tub-tie region but overlaps a first peripheral section on one side of the tub-tie region; (b5) implanting ions to form a pedestal portion of a second conductivity-type within the tub-tie region; and (b6) implanting ions of the first conductivity-type at an acute (preferably non-zero) angle −⊕ with respect to the normal to the surface to the body so as to form a conductivity-t

Abstract: The specification describes MOS transistors for analog functions which have increased output impedance. The increased output impedance is the result of reduced drain depletion width. This is accomplished without adverse effects on other device parameters. The MOS transistor structures have an implant added to the lightly doped drain (LDD) with a conductivity type opposite to that of the LDD and a doping level higher than the channel doping. The added implant confines the spread of the depletion layer and reduces its width. A relatively small confinement results in a significant increase in output impedance of the device, and a corresponding increase in transistor gain.

Abstract: A process for device fabrication in which transient enhanced diffusion (TED) is used to obtain a desired distribution of dopants in a crystalline substrate is disclosed. In the process, at least two dopants and a non-dopant are introduced into the same region of a substrate. The diffusion of the dopants in the substrate during a subsequent thermal anneal is affected by the non-dopant. The amount of non-dopant introduced into the substrate is selected to obtain, in conjunction with the subsequent thermal anneal, the desired distribution of dopants in the substrate. The concentration of the non-dopant is in the range of about 6.times.10.sup.16 atoms/cm.sup.3 to about 3.times.10.sup.21 atoms/cm.sup.3. The substrate is then annealed at a temperature in the range of about 700.degree. C. to about 950.degree. C. to obtain the desired dopant profile.

Abstract: An IC comprises a tub of a first conductivity type, at least one transistor embedded in the tub, and a first pair of isolating regions defining therebetween a tub-tie region coupled to the tub. The tub-tie region comprises a cap portion of the first conductivity type and an underlying buried pedestal portion of a second conductivity type. At least a top section of the pedestal portion is surrounded by the cap portion so that a conducting path is formed between the cap portion and the tub. In a CMOS IC tub-ties of this design are provided for both NMOS and PMOS transistors. In a preferred embodiment, the cap portion of each tub-tie comprises a relatively heavily doped central section and more lightly doped peripheral sections, both of the same conductivity type.

Abstract: An IC comprises a tub of a first conductivity type, at least one transistor embedded in the tub, and a first pair of isolating regions defining therebetween a tub-tie region coupled to the tub. The tub-tie region comprises a cap portion of the first conductivity type and an underlying buried pedestal portion of a second conductivity type. At least a top section of the pedestal portion is surrounded by the cap portion so that a conducting path is formed between the cap portion and the tub. In a CMOS IC tub-ties of this design are provided for both NMOS and PMOS transistors. In a preferred embodiment, the cap portion of each tub-tie comprises a relatively heavily doped central section and more lightly doped peripheral sections, both of the same conductivity type.

Abstract: A process for manufacturing selectively doped heterostructure field-effect transistors (SDHTs), a desired wafer structure for SDHT fabrication and a method for isolating SDHTs on the wafer are disclosed herein. The wafer has epitaxial layers grown on a substrate. The layers are: a buffer layer of GaAs, a first spacer layer of AlGaAs, a donor layer of AlGaAs, a second spacer layer of AlGaAs, a first cap layer of GaAs, an etch-stop layer of AlGaAs and a second cap layer of GaAs. A protective layer of AlGaAs may then be grown on the second cap layer to protect the second cap layer from contamination or damage. Also a superlattice may first be grown on the substrate.This invention was made with Government support under contract No. F29601-87-R-0202 awarded by the Defense Advanced Research Projects Agency, and under contract No. F33615-84-C-1570 awarded by the Air Force Wright Aeronautical Laboratories. The Government has certain rights in this invention.