Abstract: A charge pumping device includes unit cells. Each unit cell includes first and second cells, each including a charge transfer circuit, a switch controlling a charge transfer operation thereof, and a charge storage circuit having a first end connected to an output terminal of the charge transfer circuit. The switch of the first and second cell is controlled by a first and second clock and the output terminal of the second and first cell, respectively. The first and second clocks are inputted to a second end of the charge storage circuit of the second and first cells, respectively. A first interface circuit connects first and second cells of a first unit cell to second and first cells of a second unit cell, respectively. Output terminals of a final unit cell connect to a load capacitor. Input terminals of an initial unit cell connect to a supply voltage.

Abstract: A semiconductor memory device having a plurality of laser fuses is provided. In the semiconductor memory device, the plurality of laser fuses include a first region including the ends of one side of the plurality of laser fuses, a second region including the ends of the other side of the plurality of laser fuses, and a fusing region in which the plurality of laser fuses are fused. Since the laser fuses included in the fusing region are inclined so as to have a predetermined angle with the parts thereof included in the first and the second regions, the overall area and width of the fusing region are reduced.

Abstract: A memory device includes multiple memory banks that share an IO sense amplifier so that the number of sense amplifiers and the number of data lines coupled to the sense amplifiers is decreased and the area of a chip is reduced. In one embodiment, the memory device includes a plurality of memory banks, a plurality of global IO lines in the memory banks for transmitting data from the memory banks, and a plurality of IO sense amplifiers. Each sense amplifier is shared by at least two adjacent memory banks, for selectively sensing and amplifying data received from the global IO lines.

Abstract: The present invention provides delay locked loop circuits, phase detectors and methods for producing a delayed signal from a periodic input signal. An intermediate delay signal as well as an input signal and a delayed output signal are provided to a delay control circuit that controls the delay of a delay circuit based on a comparison of the input signal and output signal following a transition of the intermediate signal. The apparatus and methods of the present invention may thereby be able to distinguish between a case in which tTOTAL=T and tTOTAL=2T to reduce the potential for locking in a false state.

Abstract: A random access memory device provides high speed access by utilizing a divided precharge control scheme to reduce the loading on equalization signal lines. The equalization lines are driven at voltages which are greater than the internal operating voltage of the device, thereby reducing the row precharge time and further increasing the access speed. The device includes a plurality of bit line pairs for transferring data from memory cells. Each bit line pair is coupled to a bit line equalization circuit which includes a pair of precharge transistors that precharge the bit lines in response to a first bit line equalization signal, and an equalization transistor that equalizes the voltage of the bit lines in response to a second bit line equalization signal. The first bit line equalization signal is preferably driven at a boost voltage level, and the second bit line equalization signal is preferably driven at an external voltage level.

Abstract: A back bias generator for a semiconductor device improves refresh characteristics, reduces leakage current, and increases back bias supply capacity in a DRAM having a triple well structure by applying a well bias voltage to the bulk of an NMOS transfer transistor. The back bias generator includes a well bias generator that generates the well bias voltage before the pumping voltage is applied to the transfer transistor. The well bias provides a back bias to a parasitic NPN transistor formed in the triple well of the NMOS transfer transistor, thereby preventing leakage through the NPN into the substrate. The well bias is also applied to the bulk of a clamp transistor that initializes a pumping capacitor.