Abstract: An anti-reflective coating for use in the fabrication of a semiconductor device includes a thin oxide layer and an overlying layer of silicon oxynitride. The anti-reflective layer is advantageously used in the fabrication of FLASH memory devices which include a layer of polycrystalline silicon and an underlying layer of silicon nitride. After being used to pattern the polycrystalline silicon and silicon nitride, the anti-reflective coating is removed in a solution of hot phosphoric acid with the removal taking place before the silicon oxynitride is exposed to any elevated temperatures.

Abstract: A method of forming an improved interpoly oxide-nitride-oxide (ONO) stricture in stacked gate memory cells is provided. The top oxide layer of an interpoly ONO stack is formed using Low Pressure Chemical Vapor Deposition (LPCVD) of tetraethylorthosilicate (TEOS). As a result of the relatively low processing temperatures necessary for this step, degradation of the tunnel oxide and memory cell performance associated with high thermal-budget oxide growth processes is greatly reduced. Steam densification of the TEOS layer produces a robust top oxide for the ONO dielectric, and thus, greatly reduces erosion of the top layer TEOS during subsequent processing steps (i.e., in the context of a memory array embedded in CMOS core technology).

Abstract: A new method of forming the dielectric layer of an integrated circuit using metal layout is described. An insulating layer is formed over semiconductor device structures in and on a semiconductor substrate. Metal lines are formed overlying the insulating layer wherein the metal line mask is modified so that narrow trenches with constant width and depth are etched surrounding the metal lines and the remaining metal areas are not etched away but are left as dummy metal areas. A dielectric layer is deposited over the metal lines and dummy metal areas wherein voids are formed within the trenches between metal lines and wherein the top surface of the dielectric layer is planarized. The voids act to release system stress and to lower capacitance between the metal lines.

Abstract: A manufacturing system and method for processing semiconductor wafers through a plurality of processing stations that perform manufacturing operations on wafers includes a plurality of processing stations, each of which are capable of performing at least one processing operation of a wafer, each of the processing stations having a controlled environment for processing the wafers, and a branched track providing a surface leading to each of said processing stations. On the track there are provided a plurality of guided transport vehicles adapted to travel between the process stations. A plurality of wafer carriers, each adapted to support a single wafer and be carried by the transport vehicles, are part of the system. An interface is provided at each processing station to introduce the wafer from the box into the clean environment of the process station, and subsequently return the box and wafer to the transport vehicle.

Abstract: A manufacturing system for processing semiconductor wafers through a plurality of processing stations that perform manufacturing operations on wafers includes a plurality of processing stations, each of which are capable of performing at least one processing operation of a wafer, each of the processing stations having a controlled environment for processing the wafers, and a branched track providing a surface leading to each of said processing stations. On the track there are provided a plurality of guided transport vehicles adapted to travel between the process stations. A plurality of wafer carriers, each adapted to support a single wafer and be carried by the transport vehicles, are part of the system. An interface is provided at each processing station to introduce the wafer from the box into the clean environment of the process station, and subsequently return the box and wafer to the transport vehicle.