Patents by Inventor Hong-Jang Wu

Hong-Jang Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of fabricating field effect transistor having non-orthogonal gate electrode
    Patent number: 11211323
    Abstract: The present disclosure provides a device includes a first gate structure segment and a collinear second gate structure segment, as well as a third gate structure segment and a collinear fourth gate structure segment. An interconnection extends from the first gate structure segment to the fourth gate structure segment. The interconnection is disposed above the first gate structure segment and the fourth gate structure segment. The interconnection may be formed on or co-planar with a contact layer of the semiconductor device.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chu Liu, Shiao-Chian Yeh, Hong-Jang Wu, Kuei-Shun Chen
  • METHOD OF FABRICATING FIELD EFFECT TRANSISTOR HAVING NON-ORTHOGONAL GATE ELECTRODE
    Publication number: 20190252308
    Abstract: The present disclosure provides a device includes a first gate structure segment and a collinear second gate structure segment, as well as a third gate structure segment and a collinear fourth gate structure segment. An interconnection extends from the first gate structure segment to the fourth gate structure segment. The interconnection is disposed above the first gate structure segment and the fourth gate structure segment. The interconnection may be formed on or co-planar with a contact layer of the semiconductor device.
    Type: Application
    Filed: April 29, 2019
    Publication date: August 15, 2019
    Inventors: Chia-Chu Liu, Shiao-Chian Yeh, Hong-Jang Wu, Kuei-Shun Chen
  • Method of fabricating field effect transistor having non-orthogonal gate electrode
    Patent number: 10276488
    Abstract: The present disclosure provides a device includes a first gate structure segment and a collinear second gate structure segment, as well as a third gate structure segment and a collinear fourth gate structure segment. An interconnection extends from the first gate structure segment to the fourth gate structure segment. The interconnection is disposed above the first gate structure segment and the fourth gate structure segment. The interconnection may be formed on or co-planar with a contact layer of the semiconductor device.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Chu Liu, Shiao-Chian Yeh, Hong-Jang Wu, Kuei-Shun Chen
  • SEMICONDUCTOR DEVICE HAVING NON-ORTHOGONAL ELEMENT
    Publication number: 20180025968
    Abstract: The present disclosure provides a device includes a first gate structure segment and a collinear second gate structure segment, as well as a third gate structure segment and a collinear fourth gate structure segment. An interconnection extends from the first gate structure segment to the fourth gate structure segment. The interconnection is disposed above the first gate structure segment and the fourth gate structure segment. The interconnection may be formed on or co-planar with a contact layer of the semiconductor device.
    Type: Application
    Filed: September 29, 2017
    Publication date: January 25, 2018
    Inventors: Chia-Chu LIU, Shiao-Chian YEH, Hong-Jang WU, Kuei-Shun CHEN
  • SEMICONDUCTOR DEVICE HAVING NON-ORTHOGONAL ELEMENT
    Publication number: 20130320451
    Abstract: The present disclosure provides a device includes a first gate structure segment and a collinear second gate structure segment, as well as a third gate structure segment and a collinear fourth gate structure segment. An interconnection extends from the first gate structure segment to the fourth gate structure segment. The interconnection is disposed above the first gate structure segment and the fourth gate structure segment. The interconnection may be formed on or co-planar with a contact layer of the semiconductor device.
    Type: Application
    Filed: June 1, 2012
    Publication date: December 5, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC")
    Inventors: Chia-Chu Liu, Shiao-Chian Yeh, Hong-Jang Wu, Kuei-Shun Chen