Patents by Inventor Hong-Jie Chen
Hong-Jie Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12155111Abstract: An electronic package and a method of manufacturing an electronic package are provided. The electronic package includes a carrier, an antenna substrate, and an electronic component. The carrier has a first surface and a second surface. The antenna substrate includes a resonant cavity and is disposed over the first surface. The antenna substrate is closer to the first surface than the second surface of the carrier. The electronic component is disposed between the antenna substrate and the second surface of the carrier.Type: GrantFiled: December 30, 2021Date of Patent: November 26, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chung Ju Yu, Shao-Lun Yang, Chun-Hung Yeh, Hong Jie Chen, Tsung-Wei Lu, Wei Shuen Kao
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Patent number: 11811957Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package comprises a substrate, an antenna, and an active component. The antenna is disposed at least partially within the substrate. The active component is disposed on the substrate and electrically connected to the antenna. A location of the antenna is configured to be adjustable with respect to a location of the active component.Type: GrantFiled: May 19, 2021Date of Patent: November 7, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yuanhao Yu, Chung Ju Yu, Jui-Hsien Wang, Chai-Chi Lin, Hong Jie Chen
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Publication number: 20230216174Abstract: An electronic package and a method of manufacturing an electronic package are provided. The electronic package includes a carrier, an antenna substrate, and an electronic component. The carrier has a first surface and a second surface. The antenna substrate includes a resonant cavity and is disposed over the first surface. The antenna substrate is closer to the first surface than the second surface of the carrier. The electronic component is disposed between the antenna substrate and the second surface of the carrier.Type: ApplicationFiled: December 30, 2021Publication date: July 6, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chung Ju YU, Shao-Lun YANG, Chun-Hung YEH, Hong Jie CHEN, Tsung-Wei LU, Wei Shuen KAO
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Publication number: 20220377161Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package comprises a substrate, an antenna, and an active component. The antenna is disposed at least partially within the substrate. The active component is disposed on the substrate and electrically connected to the antenna. A location of the antenna is configured to be adjustable with respect to a location of the active component.Type: ApplicationFiled: May 19, 2021Publication date: November 24, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yuanhao YU, Chung Ju YU, Jui-Hsien WANG, Chai-Chi LIN, Hong Jie CHEN
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Publication number: 20220373670Abstract: At least some embodiments of the present disclosure relate to a wearable device. The wearable device comprises a substrate, a detecting module disposed on the substrate, and a control module disposed on the substrate. The control module is electrically connected to the detecting module. The control module is configured to receive a signal from the detecting module and to control the wearable device in response to the signal.Type: ApplicationFiled: May 19, 2021Publication date: November 24, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yuanhao YU, Chung Ju YU, Wei-Fan WU, Chai-Chi LIN, Hong Jie CHEN
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Patent number: 10797004Abstract: A semiconductor device package includes: (1) a lead frame including a connection element and multiple leads; (2) a package body encapsulating the lead frame, wherein the package body includes a lower surface and an upper surface opposite to the lower surface, the package body includes a cavity exposing at least one of the leads; (3) at least one conductive via disposed in the cavity of the package body, electrically connected to the connection element, and exposed from the upper surface of the package body; and (4) a conductive layer disposed on the upper surface of the package body and the conductive via.Type: GrantFiled: May 23, 2019Date of Patent: October 6, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Shao-Lun Yang, Yu-Shun Hsieh, Chia Yi Cheng, Hong Jie Chen, Shih Yu Huang
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Publication number: 20190279941Abstract: A semiconductor device package includes: (1) a lead frame including a connection element and multiple leads; (2) a package body encapsulating the lead frame, wherein the package body includes a lower surface and an upper surface opposite to the lower surface, the package body includes a cavity exposing at least one of the leads; (3) at least one conductive via disposed in the cavity of the package body, electrically connected to the connection element, and exposed from the upper surface of the package body; and (4) a conductive layer disposed on the upper surface of the package body and the conductive via.Type: ApplicationFiled: May 23, 2019Publication date: September 12, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Shao-Lun YANG, Yu-Shun HSIEH, Chia Yi CHENG, Hong Jie CHEN, Shih Yu HUANG
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Patent number: 10312198Abstract: A semiconductor device package includes a lead frame, an electronic component, a package body, at least one conductive via and a conductive layer. The lead frame includes a paddle, a connection element and a plurality of leads. The electronic component is disposed on the paddle. The package body encapsulates the electronic component and the lead frame. The at least one conductive via is disposed in the package body, electrically connected to the connection element, and exposed from the package body. The conductive layer is disposed on the package body and the conductive via.Type: GrantFiled: October 20, 2017Date of Patent: June 4, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Shao-Lun Yang, Yu-Shun Hsieh, Chia Yi Cheng, Hong Jie Chen, Shih Yu Huang
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Publication number: 20190122992Abstract: A semiconductor device package includes a lead frame, an electronic component, a package body, at least one conductive via and a conductive layer. The lead frame includes a paddle, a connection element and a plurality of leads. The electronic component is disposed on the paddle. The package body encapsulates the electronic component and the lead frame. The at least one conductive via is disposed in the package body, electrically connected to the connection element, and exposed from the package body. The conductive layer is disposed on the package body and the conductive via.Type: ApplicationFiled: October 20, 2017Publication date: April 25, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Shao-Lun YANG, Yu-Shun HSIEH, Chia Yi CHENG, Hong Jie CHEN, Shih Yu HUANG
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Patent number: 7475305Abstract: A method to optimize a data strobe for a multiple circuit, automatic test system is achieved. The method comprises, first, probing, in parallel, a circuit group wherein the circuit group comprises a plurality of circuits. Next, a data strobe of an automatic test system is initialized to a strobe set point relative to a system clock cycle. Next, the function of each of the circuits is partially tested, in parallel, using the strobe set point. Next, the circuit yield of the circuit group from the step of partially testing at the strobe set point is logged. Next, the data strobe is updated to a new strobe set point. Next, the steps of testing, logging, and updating are repeated until a specified range of strobe set points is completed. Finally, the data strobe is set for the circuit group to the strobe set point associated with the highest circuit yield.Type: GrantFiled: July 5, 2005Date of Patent: January 6, 2009Assignee: Etron Technology, Inc.Inventors: Tah-Kang Joseph Ting, Shih-Hsing Wang, Hong-Jie Chen
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Publication number: 20050243613Abstract: A method to optimize a data strobe for a multiple circuit, automatic test system is achieved. The method comprises, first, probing, in parallel, a circuit group wherein the circuit group comprises a plurality of circuits. Next, a data strobe of an automatic test system is initialized to a strobe set point relative to a system clock cycle. Next, the function of each of the circuits is partially tested, in parallel, using the strobe set point. Next, the circuit yield of the circuit group from the step of partially testing at the strobe set point is logged. Next, the data strobe is updated to a new strobe set point. Next, the steps of testing, logging, and updating are repeated until a specified range of strobe set points is completed. Finally, the data strobe is set for the circuit group to the strobe set point associated with the highest circuit yield.Type: ApplicationFiled: July 5, 2005Publication date: November 3, 2005Inventors: Tah-Kang Joseph Ting, Shih-Hsing Wang, Hong-Jie Chen
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Patent number: 6943044Abstract: A method to optimize a data strobe for a multiple circuit, automatic test system is achieved. The method comprises, first, probing, in parallel, a circuit group wherein the circuit group comprises a plurality of circuits. Next, a data strobe of an automatic test system is initialized to a strobe set point relative to a system clock cycle. Next, the function of each of the circuits is partially tested, in parallel, using the strobe set point. Next, the circuit yield of the circuit group from the step of partially testing at the strobe set point is logged. Next, the data strobe is updated to a new strobe set point. Next, the steps of testing, logging, and updating are repeated until a specified range of strobe set points is completed. Finally, the data strobe is set for the circuit group to the strobe set point associated with the highest circuit yield.Type: GrantFiled: June 11, 2002Date of Patent: September 13, 2005Assignee: Etron Technology, Inc.Inventors: Tah-Kang Joseph Ting, Shih-Hsing Wang, Hong-Jie Chen