Abstract: A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.

Abstract: Methods and apparatus are provided for chip aware thermal policies. The thermal performance mapping information is generated. The process obtains a set of process-dependent power data for each process corner of a semiconductor chip, profiles performance data, and selects an operating thermal policy based on the performance data. The thermal policy, based on the process-dependent power data is a mapping formula, or a combination of a mapping formula and a mapping table. The chip aware thermal control is based on process-dependent power data of process corners. The mapping information of process-dependent power data to a corresponding thermal policy is stored in a memory. A thermal policy is applied based on the stored mapping information and an obtained process corner information. The mapping information is applied every time the thermal policy is needed or at boot-up time.

Abstract: Methods and apparatus are provided for chip aware thermal policies. In one novel aspect, the thermal performance mapping information is generated. In one embodiment, the process obtains a set of process-dependent power data for each process corner of a semiconductor chip, profiles performance data, and selects an operating thermal policy based on the performance data. The thermal policy, based on the process-dependent power data is a mapping formula, or a combination of a mapping formula and a mapping table. In another novel aspect, chip aware thermal control is based on process-dependent power data of process corners. In one embodiment, the mapping information of process-dependent power data to a corresponding thermal policy is stored in a memory. A thermal policy is applied based on the stored mapping information and an obtained process corner information. The mapping information is applied every time the thermal policy is needed or at boot-up time.

Abstract: Methods and apparatus are provided for adaptive thermal slope control for dynamic thermal management. In one novel aspect, the device monitors and obtains sampling temperatures, calculates a thermal-slope index, determines whether the calculated thermal-slope index is greater than a predefined slope threshold, adjusts a power budget based on a thermal-slope algorithm, and applies the dynamic thermal management (DTM) adaptively based on the adjusted power budget. In one embodiment, fixed slope algorithm is used. The power budget is adjusted such that an adjusted slope of temperatures stays at a constant. In another embodiment, the time prediction algorithm is used. The power budget is adjusted such that a predicted time to reach a predefined thermal threshold stays a constant. In one embodiment, the time-prediction algorithm is a time-to-target-point (T2TP) algorithm. The T2TP is obtained using a linear equation or a LOG equation.

Abstract: A transaction level (TL) system power estimation method and system are provided. The method includes inserting at least a characteristic extractor into an electronic device of a target system. The characteristic extractor extracts at least a power characteristic of the electronic device when a TL simulation is proceeding. The power characteristic provided from the characteristic extractor is converted to at least a power consumption value by using a power model. The power consumption value is recorded into a power database, for analyzing power consumption of the whole target system. In some embodiments, the TL system power estimation method and system can be applied in the target system with dynamic power management. The TL system power estimation method and system also can be used with a high-level synthesizer to develop the power-aware electronic device in a short time.

Abstract: The present invention presents an effective Cycle-count Accurate Transaction level (CCA-TLM) full bus modeling and simulation technique. Using the two-phase arbiter and master-slave models, an FSM-based Composite Master-Slave-pair and Arbiter Transaction (CMSAT) model is proposed for efficient and accurate dynamic simulations. This approach is particularly effective for bus architecture exploration and contention analysis of complex Multi-Processor System-on-Chip (MPSoC) designs.

Abstract: A transaction level (TL) system power estimation method and system are provided. The method includes inserting at least a characteristic extractor into an electronic device of a target system. The characteristic extractor extracts at least a power characteristic of the electronic device when a TL simulation is proceeding. The power characteristic provided from the characteristic extractor is converted to at least a power consumption value by using a power model. The power consumption value is recorded into a power database, for analyzing power consumption of the whole target system. In some embodiments, the TL system power estimation method and system can be applied in the target system with dynamic power management. The TL system power estimation method and system also can be used with a high-level synthesizer to develop the power-aware electronic device in a short time.