Patents by Inventor Hong-Jung Hsu

Hong-Jung Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230032032
    Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.
    Type: Application
    Filed: October 11, 2022
    Publication date: February 2, 2023
    Applicant: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu, Jian-Dong Du
  • Patent number: 11500722
    Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: November 15, 2022
    Assignee: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu, Jian-Dong Du
  • Patent number: 11455241
    Abstract: A memory management method applicable to a data storage device is provided. The memory management method includes steps of: requesting a private memory space from a host; recording a reserved memory space given by the host; dividing a mapping table into a plurality of sub-mapping tables; determining whether a capacity of the reserved memory space is sufficient to store the sub-mapping tables; and if yes, uploading the sub-mapping tables to the reserved memory space via an interface logic.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: September 27, 2022
    Assignee: Silicon Motion, Inc.
    Inventors: Hong-Jung Hsu, Huang-Hsing Wu
  • Publication number: 20220182074
    Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.
    Type: Application
    Filed: February 22, 2022
    Publication date: June 9, 2022
    Applicant: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu
  • Patent number: 11354236
    Abstract: A garbage collection method for a data storage device includes steps of: entering a background mode from a foreground mode; selecting a plurality of source data blocks from a plurality of in-use data blocks; dividing a mapping table into a plurality of sub-mapping tables and selecting one of the sub-mapping tables as a target sub-mapping table, wherein the target sub-mapping table is used to manage one of the source data blocks; selecting a destination data block from a plurality of spare data blocks; and sequentially updating a correspondence relationship of data stored in the target sub-mapping table from the source data blocks to the destination data block, wherein the updating comprises copying the data stored in the source data blocks to the destination data block.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: June 7, 2022
    Assignee: Silicon Motion, Inc.
    Inventors: Hong-Jung Hsu, Chun-Chieh Kuo
  • Publication number: 20220137874
    Abstract: The present invention provides a method for controlling a data storage device. The data storage device includes a flash memory controller and a flash memory module. The flash memory controller has a first buffer memory and a second buffer memory. The memory module has at least a first memory portion and a second memory portion. The method includes: receiving a first data from a host device; storing the first data in the first buffer memory; transmitting the first data to the first memory portion of the flash memory module from the first buffer memory; and transmitting the first data to a host memory buffer in the host device from the first buffer memory. The first data corresponds to at least a portion of a second data to be written to the second memory portion.
    Type: Application
    Filed: September 29, 2021
    Publication date: May 5, 2022
    Inventor: Hong-Jung HSU
  • Patent number: 11323133
    Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programming and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: May 3, 2022
    Assignee: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu
  • Patent number: 11269783
    Abstract: An operating method for a data storage device is provided. The operating method includes steps of: dividing a mapping table into a plurality of sub-mapping tables; receiving an access command comprising a data address and a command category; determining whether a target sub-mapping table corresponding to the data address has been cached, wherein the target sub-mapping table is one of the sub-mapping tables; and if false, reading and caching the target sub-mapping table from the sub-mapping tables.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: March 8, 2022
    Assignee: Silicon Motion, Inc.
    Inventors: Hong-Jung Hsu, Chen-Hui Hsu
  • Publication number: 20210248036
    Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.
    Type: Application
    Filed: April 28, 2021
    Publication date: August 12, 2021
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu, Jian-Dong Du
  • Patent number: 11030042
    Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: June 8, 2021
    Assignee: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu, Jian-Dong Du
  • Patent number: 10846173
    Abstract: A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least a first super block and at least a second super block of the flash memory chips; and allocating the second super block to store a plurality of temporary parities generated when data is written into the first super block.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: November 24, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu
  • Publication number: 20200304148
    Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programming and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.
    Type: Application
    Filed: June 9, 2020
    Publication date: September 24, 2020
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu
  • Patent number: 10771091
    Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: September 8, 2020
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu
  • Publication number: 20200233745
    Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.
    Type: Application
    Filed: April 7, 2020
    Publication date: July 23, 2020
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu, Jian-Dong Du
  • Publication number: 20200226062
    Abstract: A garbage collection method for a data storage device includes steps of: entering a background mode from a foreground mode; selecting a plurality of source data blocks from a plurality of in-use data blocks; dividing a mapping table into a plurality of sub-mapping tables and selecting one of the sub-mapping tables as a target sub-mapping table, wherein the target sub-mapping table is used to manage one of the source data blocks; selecting a destination data block from a plurality of spare data blocks; and sequentially updating a correspondence relationship of data stored in the target sub-mapping table from the source data blocks to the destination data block, wherein the updating comprises copying the data stored in the source data blocks to the destination data block.
    Type: Application
    Filed: March 30, 2020
    Publication date: July 16, 2020
    Inventors: HONG-JUNG HSU, Chun-Chieh Kuo
  • Patent number: 10713115
    Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: July 14, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu, Jian-Dong Du
  • Publication number: 20200218650
    Abstract: A memory management method applicable to a data storage device is provided. The memory management method includes steps of: requesting a private memory space from a host; recording a reserved memory space given by the host; dividing a mapping table into a plurality of sub-mapping tables; determining whether a capacity of the reserved memory space is sufficient to store the sub-mapping tables; and if yes, uploading the sub-mapping tables to the reserved memory space via an interface logic.
    Type: Application
    Filed: March 18, 2020
    Publication date: July 9, 2020
    Inventors: HONG-JUNG HSU, HUANG-HSING WU
  • Publication number: 20200218667
    Abstract: An operating method for a data storage device is provided. The operating method includes steps of: dividing a mapping table into a plurality of sub-mapping tables; receiving an access command comprising a data address and a command category; determining whether a target sub-mapping table corresponding to the data address has been cached, wherein the target sub-mapping table is one of the sub-mapping tables; and if false, reading and caching the target sub-mapping table from the sub-mapping tables.
    Type: Application
    Filed: March 17, 2020
    Publication date: July 9, 2020
    Inventors: HONG-JUNG HSU, CHEN-HUI HSU
  • Patent number: 10678685
    Abstract: A memory management method applicable to a data storage device is provided. The memory management method includes steps of: requesting a private memory space from a host; recording a reserved memory space given by the host; dividing a mapping table into a plurality of sub-mapping tables; determining whether a capacity of the reserved memory space is sufficient to store the sub-mapping tables; and if yes, uploading the sub-mapping tables to the reserved memory space via an interface logic.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: June 9, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Hong-Jung Hsu, Huang-Hsing Wu
  • Patent number: 10657048
    Abstract: A garbage collection method for a data storage device includes steps of: entering a background mode from a foreground mode; selecting a plurality of source data blocks from a plurality of in-use data blocks; dividing a mapping table into a plurality of sub-mapping tables and selecting one of the sub-mapping tables as a target sub-mapping table, wherein the target sub-mapping table is used to manage one of the source data blocks; selecting a destination data block from a plurality of spare data blocks; and sequentially updating a correspondence relationship of data stored in the target sub-mapping table from the source data blocks to the destination data block, wherein the updating comprises copying the data stored in the source data blocks to the destination data block.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: May 19, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Hong-Jung Hsu, Chun-Chieh Kuo