Patents by Inventor Hong-Jyh Li
Hong-Jyh Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7964460Abstract: A CMOS device includes high k gate dielectric materials. A PMOS device includes a gate that is implanted with an n-type dopant. The NMOS device may be doped with either an n-type or a p-type dopant. The work function of the CMOS device is set by the material selection of the gate dielectric materials. A polysilicon depletion effect is reduced or avoided.Type: GrantFiled: April 25, 2008Date of Patent: June 21, 2011Assignee: Infineon Technologies AGInventor: Hong-Jyh Li
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Patent number: 7821627Abstract: Methods and systems for fabricating and testing semiconductor devices are disclosed. In one embodiment, a method of forming a material includes providing a first workpiece, forming a material on the first workpiece using a first process condition, and measuring a defect state of the material using a test that utilizes a monochromatic light source. If the defect state is below a predetermined value, the material is formed on at least one second workpiece using the first process condition.Type: GrantFiled: June 8, 2009Date of Patent: October 26, 2010Assignee: Infineon Technologies AGInventor: Hong-Jyh Li
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Publication number: 20100219484Abstract: Methods of forming transistors and structures thereof are disclosed. A preferred embodiment comprises a semiconductor device including a workpiece, a gate dielectric disposed over the workpiece, and a thin layer of conductive material disposed over the gate dielectric. A layer of semiconductive material is disposed over the thin layer of conductive material. The layer of semiconductive material and the thin layer of conductive material comprise a gate electrode of a transistor. A source region and a drain region are formed in the workpiece proximate the gate dielectric. The thin layer of conductive material comprises a thickness of about 50 Angstroms or less.Type: ApplicationFiled: May 14, 2010Publication date: September 2, 2010Inventor: Hong-Jyh Li
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Patent number: 7755144Abstract: Semiconductor devices with transistors having different gate dielectric materials and methods of manufacture thereof are disclosed. One embodiment includes a semiconductor device including a workpiece, the workpiece including a first region and a second region proximate the first region. A first transistor is disposed in the first region of the workpiece, the first transistor having at least two first gate electrodes. A first gate dielectric is disposed proximate each of the at least two first gate electrodes, the first gate dielectric comprising a first material. A second transistor is disposed in the second region of the workpiece, the second transistor having at least two second gate electrodes. A second gate dielectric is disposed proximate each of the at least two second gate electrodes, the second gate dielectric comprising a second material. The second material is different than the first material.Type: GrantFiled: November 12, 2008Date of Patent: July 13, 2010Assignee: Infineon Technologies AGInventors: Hong-Jyh Li, Thomas Schulz
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Patent number: 7749832Abstract: Methods of forming transistors and structures thereof are disclosed. A preferred embodiment comprises a semiconductor device including a workpiece, a gate dielectric disposed over the workpiece, and a thin layer of conductive material disposed over the gate dielectric. A layer of semiconductive material is disposed over the thin layer of conductive material. The layer of semiconductive material and the thin layer of conductive material comprise a gate electrode of a transistor. A source region and a drain region are formed in the workpiece proximate the gate dielectric. The thin layer of conductive material comprises a thickness of about 50 Angstroms or less.Type: GrantFiled: February 13, 2009Date of Patent: July 6, 2010Assignee: Infineon Technologies AGInventor: Hong-Jyh Li
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Publication number: 20100129968Abstract: Semiconductor devices with transistors having different gate dielectric materials and methods of manufacture thereof are disclosed. One embodiment includes a semiconductor device including a workpiece, the workpiece including a first region and a second region proximate the first region. A first transistor is disposed in the first region of the workpiece, the first transistor having at least two first gate electrodes. A first gate dielectric is disposed proximate each of the at least two first gate electrodes, the first gate dielectric comprising a first material. A second transistor is disposed in the second region of the workpiece, the second transistor having at least two second gate electrodes. A second gate dielectric is disposed proximate each of the at least two second gate electrodes, the second gate dielectric comprising a second material. The second material is different than the first material.Type: ApplicationFiled: November 19, 2009Publication date: May 27, 2010Inventors: Hong-Jyh Li, Thomas Schulz
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Patent number: 7709901Abstract: A CMOS device with transistors having different gate dielectric materials and a method of manufacture thereof. An aluminum-based material is used as a gate dielectric material of a PMOS device, and a hafnium-based material is used as a gate dielectric material of an NMOS device. A thin layer of silicon a few monolayers or a sub-monolayer thick is formed over the gate dielectric materials, before forming the gates. The thin layer of silicon bonds with the gate dielectric material and pins the work function of the transistors. A gate material that may comprise a metal in one embodiment is deposited over the thin layer of silicon. A CMOS device having a symmetric Vt for the PMOS and NMOS FETs is formed.Type: GrantFiled: January 22, 2008Date of Patent: May 4, 2010Assignee: Infineon Technologies AGInventor: Hong-Jyh Li
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Publication number: 20090246894Abstract: Methods and systems for fabricating and testing semiconductor devices are disclosed. In one embodiment, a method of forming a material includes providing a first workpiece, forming a material on the first workpiece using a first process condition, and measuring a defect state of the material using a test that utilizes a monochromatic light source. If the defect state is below a predetermined value, the material is formed on at least one second workpiece using the first process condition.Type: ApplicationFiled: June 8, 2009Publication date: October 1, 2009Inventor: Hong-Jyh Li
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Patent number: 7592678Abstract: CMOS devices with transistors having different gate dielectric materials and methods of manufacture thereof are disclosed. A CMOS device is formed on a workpiece having a first region and a second region. A first gate dielectric material is deposited over the second region. A first gate material is deposited over the first gate dielectric material. A second gate dielectric material comprising a different material than the first gate dielectric material is deposited over the first region of the workpiece. A second gate material is deposited over the second gate dielectric material. The first gate material, the first gate dielectric material, the second gate material, and the second gate dielectric material are then patterned to form a CMOS device having a symmetric Vt for the PMOS and NMOS FETs.Type: GrantFiled: July 21, 2005Date of Patent: September 22, 2009Assignee: Infineon Technologies AGInventor: Hong-Jyh Li
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Patent number: 7576399Abstract: A dielectric material layer is formed over a workpiece, a metal layer is formed over the dielectric material layer, and a semiconductive material layer is formed over the metal layer. The workpiece is heated, causing a top portion of the metal layer to interact with the semiconductive material layer and causing a bottom portion of the metal layer to diffuse into the dielectric material layer. The metal layer portion that interacts with the semiconductive material layer forms a silicide, and the diffused metal layer portion forms a high dielectric constant gate material having a graded concentration of the metal from the metal layer. At least the semiconductive material layer and the dielectric material layer are patterned to form a gate and a gate dielectric of a transistor device. A source region and a drain region are formed in the workpiece proximate the gate and gate dielectric.Type: GrantFiled: October 3, 2007Date of Patent: August 18, 2009Assignee: Infineon Technologies AGInventor: Hong-Jyh Li
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Patent number: 7570353Abstract: Methods and systems for fabricating and testing semiconductor devices are disclosed. In one embodiment, a method of forming a material includes providing a first workpiece, forming a material on the first workpiece using a first process condition, and measuring a defect state of the material using a test that utilizes a monochromatic light source. If the defect state is below a predetermined value, the material is formed on at least one second workpiece using the first process condition.Type: GrantFiled: December 16, 2005Date of Patent: August 4, 2009Assignee: Infineon Technologies AGInventor: Hong-Jyh Li
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Publication number: 20090166752Abstract: A first gate dielectric of a first transistor is disposed over a workpiece in a first region, and a second gate dielectric of a second transistor is disposed over the workpiece in a second region. The second gate dielectric comprises a different material than the first gate dielectric. A first dopant-bearing metal comprising a first dopant is disposed in recessed regions of the workpiece proximate the first gate dielectric, and a second dopant-bearing metal comprising a second dopant is disposed in recessed regions of the workpiece proximate the second gate dielectric. A first doped region comprising the first dopant is disposed in the workpiece adjacent the first dopant-bearing metal. A second doped region comprising the second dopant is disposed in the workpiece adjacent the second dopant-bearing metal. The dopant-bearing metals and the doped regions comprise source and drain regions of the first and second transistors.Type: ApplicationFiled: March 2, 2009Publication date: July 2, 2009Inventor: Hong-Jyh Li
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Publication number: 20090146217Abstract: Methods of forming transistors and structures thereof are disclosed. A preferred embodiment comprises a semiconductor device including a workpiece, a gate dielectric disposed over the workpiece, and a thin layer of conductive material disposed over the gate dielectric. A layer of semiconductive material is disposed over the thin layer of conductive material. The layer of semiconductive material and the thin layer of conductive material comprise a gate electrode of a transistor. A source region and a drain region are formed in the workpiece proximate the gate dielectric. The thin layer of conductive material comprises a thickness of about 50 Angstroms or less.Type: ApplicationFiled: February 13, 2009Publication date: June 11, 2009Inventor: Hong-Jyh Li
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Patent number: 7510943Abstract: A first gate dielectric of a first transistor is disposed over a workpiece in a first region, and a second gate dielectric of a second transistor is disposed over the workpiece in a second region. The second gate dielectric comprises a different material than the first gate dielectric. A first dopant-bearing metal comprising a first dopant is disposed in recessed regions of the workpiece proximate the first gate dielectric, and a second dopant-bearing metal comprising a second dopant is disposed in recessed regions of the workpiece proximate the second gate dielectric. A first doped region comprising the first dopant is disposed in the workpiece adjacent the first dopant-bearing metal. A second doped region comprising the second dopant is disposed in the workpiece adjacent the second dopant-bearing metal. The dopant-bearing metals and the doped regions comprise source and drain regions of the first and second transistors.Type: GrantFiled: December 16, 2005Date of Patent: March 31, 2009Assignee: Infineon Technologies AGInventor: Hong-Jyh Li
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Publication number: 20090065870Abstract: Semiconductor devices with transistors having different gate dielectric materials and methods of manufacture thereof are disclosed. One embodiment includes a semiconductor device including a workpiece, the workpiece including a first region and a second region proximate the first region. A first transistor is disposed in the first region of the workpiece, the first transistor having at least two first gate electrodes. A first gate dielectric is disposed proximate each of the at least two first gate electrodes, the first gate dielectric comprising a first material. A second transistor is disposed in the second region of the workpiece, the second transistor having at least two second gate electrodes. A second gate dielectric is disposed proximate each of the at least two second gate electrodes, the second gate dielectric comprising a second material. The second material is different than the first material.Type: ApplicationFiled: November 12, 2008Publication date: March 12, 2009Inventors: Hong-Jyh Li, Thomas Schulz
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Patent number: 7495290Abstract: Methods of forming transistors and structures thereof are disclosed. A preferred embodiment comprises a semiconductor device including a workpiece, a gate dielectric disposed over the workpiece, and a thin layer of conductive material disposed over the gate dielectric. A layer of semiconductive material is disposed over the thin layer of conductive material. The layer of semiconductive material and the thin layer of conductive material comprise a gate electrode of a transistor. A source region and a drain region are formed in the workpiece proximate the gate dielectric. The thin layer of conductive material comprises a thickness of about 50 Angstroms or less.Type: GrantFiled: December 14, 2005Date of Patent: February 24, 2009Assignee: Infineon Technologies AGInventor: Hong-Jyh Li
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Publication number: 20090026555Abstract: A transistor and method of manufacturing thereof. A gate dielectric and gate are formed over a workpiece, and the source and drain regions of a transistor are recessed. The recesses are filled with a dopant-bearing metal, and a low-temperature anneal process is used to form doped regions within the workpiece adjacent the dopant-bearing metal regions. A transistor having a small effective oxide thickness and a well-controlled junction depth is formed.Type: ApplicationFiled: October 3, 2008Publication date: January 29, 2009Inventors: Hong-Jyh Li, Nirmal Chaudhary
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Patent number: 7462538Abstract: Semiconductor devices with transistors having different gate dielectric materials and methods of manufacture thereof are disclosed. One embodiment includes a semiconductor device including a workpiece, the workpiece including a first region and a second region proximate the first region. A first transistor is disposed in the first region of the workpiece, the first transistor having at least two first gate electrodes. A first gate dielectric is disposed proximate each of the at least two first gate electrodes, the first gate dielectric comprising a first material. A second transistor is disposed in the second region of the workpiece, the second transistor having at least two second gate electrodes. A second gate dielectric is disposed proximate each of the at least two second gate electrodes, the second gate dielectric comprising a second material. The second material is different than the first material.Type: GrantFiled: November 15, 2005Date of Patent: December 9, 2008Assignee: Infineon Technologies AGInventors: Hong-Jyh Li, Thomas Schulz
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Patent number: 7446379Abstract: A transistor and method of manufacturing thereof. A gate dielectric and gate are formed over a workpiece, and the source and drain regions of a transistor are recessed. The recesses are filled with a dopant-bearing metal, and a low-temperature anneal process is used to form doped regions within the workpiece adjacent the dopant-bearing metal regions. A transistor having a small effective oxide thickness and a well-controlled junction depth is formed.Type: GrantFiled: February 11, 2005Date of Patent: November 4, 2008Assignee: Infineon Technologies AGInventors: Hong-Jyh Li, Nirmal Chaudhary
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Publication number: 20080233694Abstract: A CMOS device includes high k gate dielectric materials. A PMOS device includes a gate that is implanted with an n-type dopant. The NMOS device may be doped with either an n-type or a p-type dopant. The work function of the CMOS device is set by the material selection of the gate dielectric materials. A polysilicon depletion effect is reduced or avoided.Type: ApplicationFiled: April 25, 2008Publication date: September 25, 2008Inventor: Hong-Jyh Li