Abstract: An embodiment includes: an error information processing circuit configured to generate error information according to syndrome information; and a data correction circuit configured to correct an error in data according to the syndrome information. In a test mode, only the error information processing circuit between the error information processing circuit and the data correction circuit is configured to be activated.

Abstract: A random pulse generator includes: a randomness test circuit suitable for testing randomness of a random pulse; a control circuit suitable for generating frequency control information and puke control information based on a test result of the randomness test circuit; a periodic wave generating circuit suitable for generating a periodic wave whose frequency is changed based on the frequency control information; and a pulse generating circuit suitable for generating the random pulse based on the periodic wave and the pulse control information.

Abstract: A memory device includes: a normal cell region suitable for storing write data and outputting read data; a parity cell region suitable for storing write parity bits and outputting read parity bits; a pattern generation circuit suitable for generating test data whose value is sequentially increased, and providing the test data as the write data, in a first test mode; an error correction circuit suitable for generating the write parity bits based on the write data, correcting an error of the read data based on the read parity bits, and outputting the error-corrected data; and an output circuit suitable for compressing the error-corrected data and outputting the compressed data, wherein the output circuit is further suitable for compressing the read parity bits output from the parity cell region to output the compressed data, in the first test mode.

Abstract: An electronic device according to various embodiments of the present invention can comprise: a housing including a first plate facing a first direction, a second plate facing a second direction opposite to the first direction, and a side member for encompassing a space between the first plate and the second plate; a circuit board arranged inside the housing and including at least one heating element; a first vapor chamber for receiving, through conduction, and dispersing, in at least a partial space between the first plate and the circuit board, heat released from the at least one heating element; a heat sink for receiving, through conduction, and absorbing, in at least a partial space between the circuit board and the second plate, heat released from the at least one heating element; and a fan for supplying air such that the heat absorbed by the heat sink is forcibly convected toward the outside of the electronic device. Additional various embodiments are possible.

Abstract: A memory device includes: a normal cell region suitable for storing write data and outputting read data; a parity cell region suitable for storing write parity bits and outputting read parity bits; a pattern generation circuit suitable for generating test data whose value is sequentially increased, and providing the test data as the write data, in a first test mode; an error correction circuit suitable for generating the write parity bits based on the write data, correcting an error of the read data based on the read parity bits, and outputting the error-corrected data; and an output circuit suitable for compressing the error-corrected data and outputting the compressed data, wherein the output circuit is further suitable for compressing the read parity bits output from the parity cell region to output the compressed data, in the first test mode.

Abstract: A test mode set circuit includes: a first test mode set block suitable for setting entry into a first test mode based on a clock signal and first data outputted from a non-volatile memory during a first period of a boot-up operation; and a second test mode set block suitable for setting entry into a second test mode based on the first data and second data outputted from the non-volatile memory during a second period of the boot-up operation, or setting entry into the second test mode based on a set signal generated by a combination of a command and an address during a normal operation.

Abstract: An electronic device according to various embodiments of the present invention can comprise: a housing including a first plate facing a first direction, a second plate facing a second direction opposite to the first direction, and a side member for encompassing a space between the first plate and the second plate; a circuit board arranged inside the housing and including at least one heating element; a first vapor chamber for receiving, through conduction, and dispersing, in at least a partial space between the first plate and the circuit board, heat released from the at least one heating element; a heat sink for receiving, through conduction, and absorbing, in at least a partial space between the circuit board and the second plate, heat released from the at least one heating element; and a fan for supplying air such that the heat absorbed by the heat sink is forcibly convected toward the outside of the electronic device. Additional various embodiments are possible.

Abstract: A memory device includes: a memory region including a plurality of word lines; and a refresh control block configured to: sequentially refresh the plurality of word lines in a manner such that two or more word lines are simultaneously refreshed during a first refresh operation, simultaneously refresh two or more first critical word lines corresponding to a first critical address generated by up-counting a target address during a second refresh operation, and simultaneously refresh two or more second critical word lines corresponding to a second critical address generated by down-counting the target address.

Abstract: A memory device includes: a memory region including a plurality of word lines; and a refresh control block configured to: sequentially refresh the plurality of word lines in a manner such that two or more word lines are simultaneously refreshed during a first refresh operation, simultaneously refresh two or more first critical word lines corresponding to a first critical address generated by up-counting a target address during a second refresh operation, and simultaneously refresh two or more second critical word lines corresponding to a second critical address generated by down-counting the target address.

Abstract: A test mode set circuit includes: a first test mode set block suitable for setting entry into a first test mode based on a clock signal and first data outputted from a non-volatile memory during a first period of a boot-up operation; and a second test mode set block suitable for setting entry into a second test mode based on the first data and second data outputted from the non-volatile memory during a second period of the boot-up operation, or setting entry into the second test mode based on a set signal generated by a combination of a command and an address during a normal operation.

Abstract: A semiconductor device may be provided. The semiconductor device may include an input signal generator configured to enable an input signal although a reset signal is disabled after a clock enable signal is enabled. The semiconductor device may include a self-refresh enable signal generator configured to generate a self-refresh enable signal based on the input signal.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs first to (M+1)th command/address signals (wherein, “M” denotes a natural number which is equal to or greater than two) and receives a detection signal to detect a normality/abnormality of a temperature sensor. The second semiconductor device enters a test mode in response to the (M+1)th command/address signal and compare first to Nth sensing codes (wherein, “N” denotes a natural number which is equal to or greater than two) generated by the temperature sensor with the first to Mth command/address signals to generate the detection signal. The second semiconductor device also executes a refresh operation in response to a refresh signal including a plurality of pulses whose cycle time is controlled by the first to Mth command/address signals.

Abstract: A fuse test mode detection device is disclosed, which relates to a technology for improving detection efficiency of a fuse test mode. The fuse test mode detection device includes: a fuse unit configured to scan a plurality of fuses in a boot-up operation, and output fuse data; a counter configured to count the fuse data in response to a clock signal; a decoding unit configured to output a decoding signal for controlling a fuse test mode in response to an output signal of the counter; an encoder configured to encode the output signal of the decoding unit, and output a code signal; and a comparator configured to compare the fuse data with the code signal, and output a comparison signal.

Abstract: Provided is a digital image capturing apparatus which has a reduced number of components so that manufacture thereof is simplified and manufacturing costs are reduced. The digital image capturing apparatus includes a main printed circuit board (PCB) on which a charge-coupled device (CCD) and a control component for controlling the digital image capturing apparatus are directly mounted. A lens barrel is aligned with the CCD and directly connected with the main PCB.

Abstract: Provided is an indicator display device displaying information by using an indicator, and more particularly, provided is an indicator display device having a simplified configuration and including a small module. The indicator display device includes a stepping motor; an indicator which is connected to the stepping motor and rotates by a driving force provided by the stepping motor; and an indicator position detector which detects a relative position of the indicator with regard to the stepping motor.

Abstract: Provided is an indicator display device displaying information by using an indicator, and more particularly, provided is an indicator display device having a simplified configuration and including a small module. The indicator display device includes a stepping motor; an indicator which is connected to the stepping motor and rotates by a driving force provided by the stepping motor; and an indicator position detector which detects a relative position of the indicator with regard to the stepping motor.

Abstract: A reduced-component flash assembly for a digital image capturing apparatus, and a digital image capturing apparatus including the same are provided. The digital image capturing apparatus includes a frame; a flash module including a flash lamp which is capable of emitting a flash and a flash lamp housing which contains the flash lamp; a top PCB fitted with the flash module, which is disposed on a top part of the frame, on which a flash lamp control component controlling the flash lamp is mounted, and on which a button correspondence component corresponding to a button disposed on a top part of the digital image capturing apparatus is mounted; and a main PCB which is disposed in a side part of the frame, which is electrically connected to the top PCB, and on which a control component controlling the digital image capturing apparatus is mounted.

Abstract: Provided is a digital image capturing apparatus which has a reduced number of components so that manufacture thereof is simplified and manufacturing costs are reduced. The digital image capturing apparatus includes a main printed circuit board (PCB) on which a charge-coupled device (CCD) and a control component for controlling the digital image capturing apparatus are directly mounted. A lens barrel is aligned with the CCD and directly connected with the main PCB.