Abstract: Aspects discussed herein relate to systems, apparatuses, and methods to identify, in near real-time, points of interest of viewers of a content item concurrently being transmitted in a linear stream to the viewers. A point of interest may refer to a segment of the content item that caused a surge in user reactions. During a subsequent transmission of the content item, identified points of interests may be displayed to the viewer. The viewer may select the point of interest in the content item to begin playback of the point of interest in the content item. Further, a playlist of points of interest in one or more content items may be generated for playback of the points of interest to a viewer.

Abstract: A charge pump includes: a charging unit including a first n-type transistor connected between an input terminal configured to receive an input voltage and a first node, a second n-type transistor connected between the input terminal and a second node, a first gate control element configured to control the first n-type transistor based on a first clock signal and a second gate control element configured to control the second n-type transistor based on a second clock signal having a phase opposite to the first clock signal; a first pumping capacitor including one end connected to the first node and an other end configured to receive the first clock signal; a second pumping capacitor including one end connected to the second node and an other end configured to receive the second clock signal; and an output unit.

Abstract: Provided is a semiconductor memory device. In order to permit dense integration of a high number of stacked word lines in the semiconductor memory device, a charge pump is included in the semiconductor Mary device. The charge pump makes use of a capacitor. The capacitor is implemented with respect to the dense integration. Some components are placed under the stacked word lines, and some are not under the stacked word lines. The capacity of the capacitor not under the stacked word lines is provided in part by a parallel structure.

Abstract: A server according to an embodiment of the disclosure may include at least one processor and storage, wherein the at least one processor may be configured to receive beacon information including information on at least one website from the electronic device, collect data from a first website of the at least one website based on the beacon information, generate content having a structured document format based on at least a part of the collected data, and transmit the generated content to the electronic device.

Abstract: A charge pump includes: a charging unit including a first n-type transistor connected between an input terminal configured to receive an input voltage and a first node, a second n-type transistor connected between the input terminal and a second node, a first gate control element configured to control the first n-type transistor based on a first clock signal and a second gate control element configured to control the second n-type transistor based on a second clock signal having a phase opposite to the first clock signal; a first pumping capacitor including one end connected to the first node and an other end configured to receive the first clock signal; a second pumping capacitor including one end connected to the second node and an other end configured to receive the second clock signal; and an output unit.

Abstract: A charge pump includes: a charging unit including a first n-type transistor connected between an input terminal configured to receive an input voltage and a first node, a second n-type transistor connected between the input terminal and a second node, a first gate control element configured to control the first n-type transistor based on a first clock signal and a second gate control element configured to control the second n-type transistor based on a second clock signal having a phase opposite to the first clock signal; a first pumping capacitor including one end connected to the first node and an other end configured to receive the first clock signal; a second pumping capacitor including one end connected to the second node and an other end configured to receive the second clock signal; and an output unit.

Abstract: A dynamic power control system includes an external power input terminal receiving a first output electric current from a power management circuit outside of the memory device; a variable charge pump receiving a second input voltage and a second input electric current, boosting the second input voltage to a second output voltage, and outputting the second output voltage and a second output electric current to the memory device; and a feedback controller to compare a ratio of the first output electric current to the first input electric current and a ratio of the second output electric current to the second input electric current, and to select one of the power management circuit and the variable charge pump to supply power to the memory device, according to the comparison result.

Abstract: A charge pump includes: a charging unit including a first n-type transistor connected between an input terminal configured to receive an input voltage and a first node, a second n-type transistor connected between the input terminal and a second node, a first gate control element configured to control the first n-type transistor based on a first clock signal and a second gate control element configured to control the second n-type transistor based on a second clock signal having a phase opposite to the first clock signal; a first pumping capacitor including one end connected to the first node and an other end configured to receive the first clock signal; a second pumping capacitor including one end connected to the second node and an other end configured to receive the second clock signal; and an output unit.

Abstract: A dynamic power control system includes an external power input terminal receiving a first output electric current from a power management circuit outside of the memory device; a variable charge pump receiving a second input voltage and a second input electric current, boosting the second input voltage to a second output voltage, and outputting the second output voltage and a second output electric current to the memory device; and a feedback controller to compare a ratio of the first output electric current to the first input electric current and a ratio of the second output electric current to the second input electric current, and to select one of the power management circuit and the variable charge pump to supply power to the memory device, according to the comparison result.

Abstract: A server according to an embodiment of the disclosure may include at least one processor and storage, wherein the at least one processor may be configured to receive beacon information including information on at least one website from the electronic device, collect data from a first website of the at least one website based on the beacon information, generate content having a structured document format based on at least a part of the collected data, and transmit the generated content to the electronic device. In addition, various embodiments may be possible as understood from the disclosure.

Abstract: A photonic crystal laser and a strain measuring device are provided. The photonic crystal laser includes a disk-shaped photonic crystal structure two-dimensionally disposed in a matrix on a disposition plane and a flexible substrate disposed to support the photonic crystal structure and to cover at least a side surface of the photonic crystal structure.

Abstract: Methods of operating a memory device include at least partially charging a sensing node within a page buffer of the memory device to a first precharge voltage, by sampling a trip voltage of a sensing latch within the page buffer. Thereafter, a voltage of the sensing node is boosted from the first precharge voltage to a higher second precharge voltage. Then, a voltage of the sensing node that reflects a value of data stored in a memory cell of the memory device is developed at the sensing node. The developed voltage is then transferred to the sensing latch so that data stored by the sensing latch reflects the value of data stored in the memory cell.

Abstract: A semiconductor device includes first source/drain regions disposed at both sides of a first gate structure and including dopants of a first conductivity type, counter regions being in contact with upper portions of the first source/drain regions and under both end portions of the first gate structure, and first halo regions in contact with bottom surfaces of the first source/drain regions. The counter regions include dopants of a second conductivity type that is different from the first conductivity type. The first halo regions include dopants of the second conductivity type.

Abstract: A method of driving a crack detector of an organic light emitting display device according to example embodiments includes: determining an image load of a display panel with respect to image data corresponding to an emission period of the organic light emitting display device when it is driven according to a simultaneous emission driving method, calculating a first sensing value corresponding to a power current that flows into a power supply during the emission period, determining a first crack reference value based on the image load, and determining whether the display panel is cracked by comparing the first crack reference value with the first sensing value.

Abstract: A data driver capable of displaying images with a substantially uniform brightness, an organic light emitting display device using the same, and a method of driving the organic light emitting display device. The data driver includes a plurality of current sink units for controlling predetermined currents to flow through data lines, a plurality of voltage generators for resetting values of gray scale voltages using compensation voltages generated when the predetermined currents flow, a plurality of digital-to-analog converters for selecting one gray scale voltage among the gray scale voltages as a data signal in response to bit values of the data supplied from the outside, and a plurality of switching units for supplying the data signal to the data lines. The predetermined currents may be set equal to pixel currents that correspond to a maximum brightness.

Abstract: A semiconductor package includes a package base substrate including bonding pads and a connection pads respectively on an upper surface and a lower surface of the package base substrate, four semiconductor chips attached onto the package base substrate, including a 1A semiconductor chip, a 1B semiconductor chip, a 2A semiconductor chip, and a 2B semiconductor chip, and each including a plurality of chip pads that are adjacent to a first edge of an upper surface of each of the 1A semiconductor chip, the 1B semiconductor chip, the 2A semiconductor chip, and the 2B semiconductor chip, and a bonding wire electrically connecting the chip pad and the bonding pad to each other, wherein the four semiconductor chips are disposed on the package base substrate such that first edges of the four semiconductor chips respectively face edges of the package base substrate that are different from each other.

Abstract: The present disclosure relates to an electronic device and a beacon-based searching method by the electronic device, which may store one or more data items received through a beacon signal using the wireless communication circuit, obtain information related to at least one data item related to a keyword search requested from among the one or more stored data items corresponding to a keyword search request, and display at least part of the obtained information on a screen.

Abstract: A semiconductor device includes first source/drain regions disposed at both sides of a first gate structure and including dopants of a first conductivity type, counter regions being in contact with upper portions of the first source/drain regions and under both end portions of the first gate structure, and first halo regions in contact with bottom surfaces of the first source/drain regions. The counter regions include dopants of a second conductivity type that is different from the first conductivity type. The first halo regions include dopants of the second conductivity type.

Abstract: A high voltage switch circuit of a nonvolatile memory device includes a high voltage transistor, logic, and a high voltage switch. The high voltage transistor is turned-on based on a program turn-on voltage and transfers a program voltage to a first memory block. The logic generates path selection signals based on an enable signal and switching control signals based on one of an operating parameter of the nonvolatile memory device or an access address for at least a portion of the first memory block. The enable signal is activated during a program operation on the first memory block. The high voltage switch delivers the program turn-on voltage to a gate of the high voltage transistor via one of a plurality of delivery paths based on the path selection signals. As a result, influence of a negative bias temperature instability (NBTI) generated by the program turn-on voltage is dispersed.

Abstract: A semiconductor device includes first source/drain regions disposed at both sides of a first gate structure and including dopants of a first conductivity type, counter regions being in contact with upper portions of the first source/drain regions and under both end portions of the first gate structure, and first halo regions in contact with bottom surfaces of the first source/drain regions. The counter regions include dopants of a second conductivity type that is different from the first conductivity type. The first halo regions include dopants of the second conductivity type.