Abstract: A woven information bearing device comprising a plurality of woven elements arranged to define a woven information bearing pattern, wherein the woven elements include N woven information bearing elements, N being an integer number; and wherein said N woven information bearing elements define N or more than N data elements.

Abstract: A composite information bearing device comprising an image pattern and a human readable data device. The human readable data device includes a set of human readable data symbols representing a first set of data. The first set of data includes a first data portion and a second data portion. The image pattern represents a second set of data and comprises a third data portion. One of the first or said second data portions is to form an identification code upon combination or concatenation with said third data portion, and the other one of said first or said second data portions not forming part of said identification code is to form a verification code, the verification code being related to said identification code by a scheme of operation.

Abstract: An information bearing device comprising a data bearing pattern, the data bearing pattern comprising M×N pattern defining elements which are arranged to define a set of characteristic spatial distribution properties (Îu,vM,N(x,y)), wherein the set of data comprises a plurality of discrete data and each said discrete data (ui,vi) has an associated data bearing pattern which is characteristic of said discrete data, and the set of characteristic spatial distribution properties is due to the associated data bearing patterns of said plurality of discrete data, wherein said discrete data and the associated data bearing pattern of said discrete data is related by a characteristic relation function (?k1,ui,vi(x,y), the characteristic relation function defining spatial distribution properties of said associated data bearing pattern according to said discrete data (ui,vi) and a characteristic parameter (k) that is independent of said discrete data.

Abstract: A composite device comprising a human-readable target device and a verification device in machine-readable (or non-human-readable) encoding in which the verification device is related to the target device by a predefined scheme of operation, the target device may comprise a plurality of human readable symbols. For example, the human readable symbols may be arranged into a string of symbols which is also referred to as a ‘token’ herein. The composite device is useful for applications such as authentication, automated Internet access etc.

Abstract: An apparatus (100, 1001) comprises an image capturing device (110), a light emitting device (112) for illuminating an object to be captured by the image capturing device (110), a visual guide (114) to guide a user to aim the apparatus (100, 1001) at a target authentication device (140), and a processor (102). The visual guide (114) is devised such that when the apparatus (100, is aimed at the target authentication device (140) following guidance of the visual guide (114), the brightness levels on an image of the target authentication device (140) captured by the image capturing device (110) while under illumination of the light emit ting device (112) are within a predetermined range of brightness levels to facilitate verification of authenticity with reference to the captured image of the target authentication device (140).

Abstract: A method of and an apparatus for verifying authenticity of a target authentication device comprising a reference pattern having a characteristic frequency and a security pattern, the security pattern comprises an embedded security device that is coded with phase modulation information. The method comprises extracting frequency domain data from an image of the target authentication device to facilitate verification of authenticity of the target authentication device. The method provides a very effective end expedient mechanism for verifying authenticity of a moiré or moiré like authentication device to combat counterfeiting.

Abstract: A cache within a computer system receives a partial write request and identifies a cache hit of a cache line. The cache line corresponds to the partial write request and includes existing data. In turn, the cache receives partial write data and merges the partial write data with the existing data into the cache line. In one embodiment, the existing data is “modified” or “dirty.” In another embodiment, the existing data is “shared.” In this embodiment, the cache changes the state of the cache line to indicate the storing of the partial write data into the cache line.

Abstract: A method, system and computer-usable medium are disclosed for managing prefetch streams in a virtual machine environment. Compiled application code in a first core, which comprises a Special Purpose Register (SPR) and a plurality of first prefetch engines, initiates a prefetch stream request. If the prefetch stream request cannot be initiated due to unavailability of a first prefetch engine, then an indicator bit indicating a Prefetch Stream Dispatch Fault is set in the SPR, causing a Hypervisor to interrupt the execution of the prefetch stream request. The Hypervisor then calls its associated operating system (OS), which determines prefetch engine availability for a second core comprising a plurality of second prefetch engines. If a second prefetch engine is available, then the OS migrates the prefetch stream request from the first core to the second core, where it is initiated on an available second prefetch engine.

Abstract: A method, system and computer-usable medium are disclosed for managing prefetch streams in a virtual machine environment. Compiled application code in a first core, which comprises a Special Purpose Register (SPR) and a plurality of first prefetch engines, initiates a prefetch stream request. If the prefetch stream request cannot be initiated due to unavailability of a first prefetch engine, then an indicator bit indicating a Prefetch Stream Dispatch Fault is set in the SPR, causing a Hypervisor to interrupt the execution of the prefetch stream request. The Hypervisor then calls its associated operating system (OS), which determines prefetch engine availability for a second core comprising a plurality of second prefetch engines. If a second prefetch engine is available, then the OS migrates the prefetch stream request from the first core to the second core, where it is initiated on an available second prefetch engine.

Abstract: A method, in accordance with particular embodiments, includes receiving a configuration message for configuring a first node with an IP address. The configuration message comprises a subnet portion associated with a group of nodes and a host portion associated with the first node. The method also includes detecting a second node in a routing table maintained by the first node. The method further includes determining that the second node has an IP address comprising a subnet portion matching the subnet portion of the IP address associated with the first node. The method additionally includes determining that the second node is a member of the group of nodes based on the matching subnet portion of the IP address of the second node. The method also includes transmitting a message to at least the second node identifying a service supported by the first node for the group of nodes.

Abstract: A method associated with particular embodiments comprises establishing a connection between a first node and a network composed of a plurality of nodes supporting a plurality of services. Each of the services is supported by at least one of the nodes. The method further includes receiving at a first node a frame from a second node of the plurality of nodes. The frame comprises at least two labels attached to the frame by the second node. The method also includes extracting a first label value and a second label value from the two labels. The method further includes determining that the frame was sent by the second node based on an extracted first label value and that the frame is associated with a first service based on the extracted second label value. The method additionally includes processing the frame based on both of the determinations.

Abstract: A method, medium and implementing processing system are provided in which the Operating System (OS) driver is divided into two parts, viz. an upper level OS driver and a lower level OS driver. The lower level OS driver sets up the adapter hardware and any adapter hardware work-around. The upper level OS driver is interfaced to the OS communication stack and each can be compiled separately. The upper OS driver is compiled and shipped with the OS to make sure it is compatible with the OS communication stack. The lower OS driver, in an exemplary embodiment, is compiled and stored in an adapter flash memory. The OS dynamically combines the upper and lower OS drivers together during the load time.

Abstract: An operating system of an information handling system (IHS) determines a process tree of data sharing threads in an application that the IHS executes. A load balancing manager assigns a home processor to each thread of the executing application process tree and dispatches the process tree to the home processor. The load balancing manager determines whether a particular poaching processor of a virtual or real processor group is available to execute threads of the executing application within the home processor of a processor group. If ready or run queues of a prospective poaching processor are empty, the load balancing manager may move or poach a thread or threads from the home processor ready queue to the ready queue of the prospective poaching processor. The poaching processor executes the poached threads to provide load balancing to the information handling system (IHS).

Abstract: A processor thread load balancing manager employs an operating system of an information handling system (IHS) that determines a process tree of data sharing threads in an application that the IHS executes. The load balancing manager assigns a home processor to each thread of the executing application process tree and dispatches the process tree to the home processor. The load balancing manager determines whether a particular poaching processor of a virtual or real processor group is available to execute threads of the executing application within the home processor of a processor group. If ready or run queues of a prospective poaching processor are empty, the load balancing manager may move or poach a thread or threads from the home processor ready queue to the ready queue of the prospective poaching processor. The poaching processor executes the poached threads to provide load balancing to the information handling system (IHS).

Abstract: A cache within a computer system receives a partial write request and identifies a cache hit of a cache line. The cache line corresponds to the partial write request and includes existing data. In turn, the cache receives partial write data and merges the partial write data with the existing data into the cache line. In one embodiment, the existing data is “modified” or “dirty.” In another embodiment, the existing data is “shared.” In this embodiment, the cache changes the state of the cache line to indicate the storing of the partial write data into the cache line.

Abstract: A processor thread load balancing manager employs an operating system of an information handling system (IHS) that determines a process tree of data sharing threads in an application that the IHS executes. The load balancing manager assigns a home processor to each thread of the executing application process tree and dispatches the process tree to the home processor. The load balancing manager determines whether a particular poaching processor of a virtual or real processor group is available to execute threads of the executing application within the home processor of a processor group. If ready or run queues of a prospective poaching processor are empty, the load balancing manager may move or poach a thread or threads from the home processor ready queue to the ready queue of the prospective poaching processor. The poaching processor executes the poached threads to provide load balancing to the information handling system (IHS).

Abstract: A method associated with particular embodiments comprises establishing a connection between a first node and a network composed of a plurality of nodes supporting a plurality of services. Each of the services is supported by at least one of the nodes. The method further includes receiving at a first node a frame from a second node of the plurality of nodes. The frame comprises at least two labels attached to the frame by the second node. The method also includes extracting a first label value and a second label value from the two labels. The method further includes determining that the frame was sent by the second node based on an extracted first label value and that the frame is associated with a first service based on the extracted second label value. The method additionally includes processing the frame based on both of the determinations.

Abstract: A method, in accordance with particular embodiments, includes receiving a configuration message for configuring a first node with an IP address. The configuration message comprises a subnet portion associated with a group of nodes and a host portion associated with the first node. The method also includes detecting a second node in a routing table maintained by the first node. The method further includes determining that the second node has an IP address comprising a subnet portion matching the subnet portion of the IP address associated with the first node. The method additionally includes determining that the second node is a member of the group of nodes based on the matching subnet portion of the IP address of the second node. The method also includes transmitting a message to at least the second node identifying a service supported by the first node for the group of nodes.

Abstract: An operating system of an information handling system (IHS) determines a process tree of data sharing threads in an application that the IHS executes. A load balancing manager assigns a home processor to each thread of the executing application process tree and dispatches the process tree to the home processor. The load balancing manager determines whether a particular poaching processor of a virtual or real processor group is available to execute threads of the executing application within the home processor of a processor group. If ready or run queues of a prospective poaching processor are empty, the load balancing manager may move or poach a thread or threads from the home processor ready queue to the ready queue of the prospective poaching processor. The poaching processor executes the poached threads to provide load balancing to the information handling system (IHS).

Abstract: An improved mounting system for use with display units and other devices of various sizes. A mounting system of the present invention includes a surface mounting bracket and at least one device mounting bracket. At least one of the surface mounting bracket and the at least one device mounting bracket is expandable such that it is able to accommodate and support devices of different dimensions and weights.