Abstract: A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.

Abstract: A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.

Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.

Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.

Abstract: A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.

Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.

Abstract: A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.

Abstract: A method of detecting a power level of an RF signal includes driving an internal node of a power detection circuit to a DC node voltage level, generating, based on the DC node voltage level, a first component of an output voltage on an output node of the power detection circuit, receiving the RF signal on an input node of the power detection circuit, dividing the RF signal to generate a modulation signal on the internal node, and generating, by at least partially rectifying the modulation signal, a second component of the output voltage on the power detection circuit output node.

Abstract: A method of detecting a power level of an RF signal includes driving an internal node of a power detection circuit to a DC node voltage level, generating, based on the DC node voltage level, a first component of an output voltage on an output node of the power detection circuit, receiving the RF signal on an input node of the power detection circuit, dividing the RF signal to generate a modulation signal on the internal node, and generating, by at least partially rectifying the modulation signal, a second component of the output voltage on the power detection circuit output node.

Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.

Abstract: A transmitter circuit includes an amplifier configured to output a radio frequency (RF) signal on an output node, a power detection circuit coupled with the output node and configured to generate an output voltage having a first component based on a power level of the RF signal, and a reference voltage generator configured to generate a reference voltage. A comparator is configured to receive the output voltage and the reference voltage, an analog-to-digital converter (ADC) is coupled between the comparator and the amplifier, and the amplifier is configured to adjust the power level of the RF signal responsive to an output of the ADC.

Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.

Abstract: A transmission frontend includes a modulator configured to generate a modulated signal. A first selectable path is electrically coupled to the modulator and is configured to generate a first signal having a first power level. A second selectable path is electrically coupled to the modulator and is configured to generate a second signal having a second power level. The first power level is greater than the second power level. A transformer is electrically coupled to each of the first selectable path and the second selectable path. An antenna is electrically coupled to the transformer.

Abstract: A transmitter circuit includes an amplifier configured to output a radio frequency (RF) signal on an output node, a power detection circuit coupled with the output node and configured to generate an output voltage having a first component based on a power level of the RF signal, and a reference voltage generator configured to generate a reference voltage. A comparator is configured to receive the output voltage and the reference voltage, an analog-to-digital converter (ADC) is coupled between the comparator and the amplifier, and the amplifier is configured to adjust the power level of the RF signal responsive to an output of the ADC.

Abstract: A circuit includes a first device between a first input node and an internal node, a second device between a second input node and the internal node, a third device between the internal node and ground, a fourth device between the internal node and an output node, and a fifth device between the output node and ground. The second and third devices generate a direct current (DC) voltage on the internal node by dividing a bias voltage on the second input node. The fourth device generates, from the DC voltage, a first component of an output voltage on the output node. The first and third devices generate a modulation signal on the internal node by dividing a radio frequency (RF) signal on the first input node. The fifth device rectifies the modulation signal to generate a second output voltage component.

Abstract: A transmission frontend includes a modulator configured to generate a modulated signal. A first selectable path is electrically coupled to the modulator and is configured to generate a first signal having a first power level. A second selectable path is electrically coupled to the modulator and is configured to generate a second signal having a second power level. The first power level is greater than the second power level. A transformer is electrically coupled to each of the first selectable path and the second selectable path. An antenna is electrically coupled to the transformer.

Abstract: A circuit includes a first device between a first input node and an internal node, a second device between a second input node and the internal node, a third device between the internal node and ground, a fourth device between the internal node and an output node, and a fifth device between the output node and ground. The second and third devices generate a direct current (DC) voltage on the internal node by dividing a bias voltage on the second input node. The fourth device generates, from the DC voltage, a first component of an output voltage on the output node. The first and third devices generate a modulation signal on the internal node by dividing a radio frequency (RF) signal on the first input node. The fifth device rectifies the modulation signal to generate a second output voltage component.

Abstract: A tunable matching circuit for use with ultra-low power RF receivers is described to support a variety of RF communication bands. A switched-capacitor array and a switched-resistor array are used to adjust the input impedance presented by the operating characteristics of transistors in an ultra-low-power mode. An RF sensor may be used to monitor performance of the tunable matching circuit and thereby determine optimal setting of the digital control word that drives the switched-capacitor array and switched-resistor array. An effective match over a significant bandwidth is achievable. The optimal matching configuration may be updated at any time to adjust to changing operating conditions. Memory may be used to store the optimal matching configurations of the switched capacitor array and switched resistor array.

Abstract: A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.

Abstract: A tunable matching circuit for use with ultra-low power RF receivers is described to support a variety of RF communication bands. A switched-capacitor array and a switched-resistor array are used to adjust the input impedance presented by the operating characteristics of transistors in an ultra-low-power mode. An RF sensor may be used to monitor performance of the tunable matching circuit and thereby determine optimal setting of the digital control word that drives the switched-capacitor array and switched-resistor array. An effective match over a significant bandwidth is achievable. The optimal matching configuration may be updated at any time to adjust to changing operating conditions. Memory may be used to store the optimal matching configurations of the switched capacitor array and switched resistor array.