Patents by Inventor Hong Mao

Hong Mao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250226291
    Abstract: The present disclosure describes a buried conductive structure in a semiconductor substrate and a method for forming the structure. The structure includes an epitaxial region disposed on a substrate and adjacent to a nanostructured gate layer and a nanostructured channel layer, a first silicide layer disposed within a top portion of the epitaxial region, and a first conductive structure disposed on a top surface of the first silicide layer. The structure further includes a second silicide layer disposed within a bottom portion of the epitaxial region and a second conductive structure disposed on a bottom surface of the second silicide layer and traversing through the substrate, where the second conductive structure includes a first metal layer in contact with the second silicide layer and a second metal layer in contact with the first metal layer.
    Type: Application
    Filed: March 24, 2025
    Publication date: July 10, 2025
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kan-Ju LIN, Lin-Yu Huang, Min-Hsuan Lu, Wei-Yip Loh, Hong-Mao Lee, Harry Chien
  • Patent number: 12327788
    Abstract: A method for manufacturing a semiconductor device includes: forming a lower metal contact in a trench of a first dielectric structure, the lower metal contact having a height less than a depth of the trench and being made of a first metal material; forming an upper metal contact to fill the trench and to be in contact with the lower metal contact, the upper metal contact being formed of a second metal material different from the first metal material and having a bottom surface with a dimension the same as a dimension of a top surface of the lower metal contact; forming a second dielectric structure on the first dielectric structure; and forming a via contact penetrating through the second dielectric structure to be electrically connected to the upper metal contact, the via contact being formed of a metal material the same as the second metal material.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: June 10, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shuen-Shin Liang, Chia-Hung Chu, Po-Chin Chang, Tzu-Pei Chen, Ken-Yu Chang, Hung-Yi Huang, Harry Chien, Wei-Yip Loh, Chun-I Tsai, Hong-Mao Lee, Sung-Li Wang, Pinyen Lin
  • Publication number: 20250167047
    Abstract: A semiconductor device is disclosed. The device includes a source/drain feature formed over a substrate. A dielectric layer formed over the source/drain feature. A contact trench formed through the dielectric layer to expose the source/drain feature. A titanium nitride (TiN) layer deposited in the contact trench and a cobalt layer deposited over the TiN layer in the contact trench.
    Type: Application
    Filed: January 17, 2025
    Publication date: May 22, 2025
    Inventors: Chun-Hsien Huang, Wei-Jung Lin, Hsien-Lung Yang, Yu-Kai Chen, Hong-Mao Lee
  • Patent number: 12272621
    Abstract: The present disclosure describes a buried conductive structure in a semiconductor substrate and a method for forming the structure. The structure includes an epitaxial region disposed on a substrate and adjacent to a nanostructured gate layer and a nanostructured channel layer, a first silicide layer disposed within a top portion of the epitaxial region, and a first conductive structure disposed on a top surface of the first silicide layer. The structure further includes a second silicide layer disposed within a bottom portion of the epitaxial region and a second conductive structure disposed on a bottom surface of the second silicide layer and traversing through the substrate, where the second conductive structure includes a first metal layer in contact with the second silicide layer and a second metal layer in contact with the first metal layer.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kan-Ju Lin, Lin-Yu Huang, Min-Hsuan Lu, Wei-Yip Loh, Hong-Mao Lee, Harry Chien
  • Patent number: 12211747
    Abstract: A semiconductor device is disclosed. The device includes a source/drain feature formed over a substrate. A dielectric layer formed over the source/drain feature. A contact trench formed through the dielectric layer to expose the source/drain feature. A titanium nitride (TiN) layer deposited in the contact trench and a cobalt layer deposited over the TiN layer in the contact trench.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Hsien Huang, Hong-Mao Lee, Hsien-Lung Yang, Yu-Kai Chen, Wei-Jung Lin
  • Publication number: 20240405023
    Abstract: A semiconductor device includes a semiconductor fin protruding from a substrate. The semiconductor device includes a P-type device over the semiconductor fin and an N-type device over the semiconductor fin. The P-type device includes a first source/drain (S/D) feature adjacent a first gate structure. The P-type device includes a dipole layer over the first S/D feature, where the dipole layer includes a first metal and a second metal different from the first metal. The P-type device further includes a first silicide layer over the dipole layer, where the first silicide layer includes the first metal. The N-type device includes a second S/D feature adjacent a second gate structure. The N-type device further includes a second silicide layer directly contacting the second S/D feature, where the second silicide layer includes the first metal, and where a composition of the second silicide layer is different from that of the dipole layer.
    Type: Application
    Filed: May 31, 2023
    Publication date: December 5, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuen-Shin LIANG, Hong-Mao Lee, Sung-Li Wang, Yan-Ming Tsai, Po-Chin Chang, Wei-Yip Loh, Harry CHIEN, Pei-Hua Lee
  • Publication number: 20240398969
    Abstract: The present invention provides an antibody-drug conjugate (ADC) for treating HIV infection, comprising an antibody that binds to CD4, conjugated via a linker to a small-molecule drug capable of treating or preventing HIV infection.
    Type: Application
    Filed: May 31, 2024
    Publication date: December 5, 2024
    Inventors: Chu-Ling WEN, Yu-Hong MAO, Chin-Ming CHANG
  • Publication number: 20240379758
    Abstract: A semiconductor device structure and methods of forming the same are described. In some embodiments, the structure includes an N-type source/drain epitaxial feature disposed over a substrate, a P-type source/drain epitaxial feature disposed over the substrate, a first silicide layer disposed directly on the N-type source/drain epitaxial feature, and a second silicide layer disposed directly on the P-type source/drain epitaxial feature. The first and second silicide layers include a first metal, and the second silicide layer is substantially thicker than the first silicide layer. The structure further includes a third silicide layer disposed directly on the first silicide layer and a fourth silicide layer disposed directly on the second silicide layer. The third and fourth silicide layer include a second metal different from the first metal, and the third silicide layer is substantially thicker than the fourth silicide layer.
    Type: Application
    Filed: May 11, 2023
    Publication date: November 14, 2024
    Inventors: Wei-Yip LOH, Hong-Mao LEE, Harry CHIEN, Po-Chin CHANG, Sung-Li WANG, Jhih-Rong HUANG, Tzer-Min SHEN, Chih-Wei CHANG
  • Publication number: 20240379759
    Abstract: A semiconductor device includes a first transistor, a second transistor, a first metal silicide layer, a second metal silicide layer, and an isolation structure. The first transistor includes a first channel layer, a first gate structure, and first source/drain epitaxy structures. The second transistor includes a second channel layer, a second gate structure, and second source/drain epitaxy structures. The first metal silicide layer is over one of the first source/drain epitaxy structures. The second metal silicide layer is over one of the second source/drain epitaxy structures. The isolation structure covers the one of the first source/drain epitaxy structures and the one of the second source/drain epitaxy structures, wherein in a cross-sectional view, the one of the first source/drain epitaxy structures is separated from the isolation structure through the first metal silicide layer, while the one of the second source/drain epitaxy structures is in contact with the isolation structure.
    Type: Application
    Filed: May 10, 2023
    Publication date: November 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Yip LOH, Li-Wei CHU, Hong-Mao LEE, Hung-Chang HSU, Hung-Hsu CHEN, Harry CHIEN, Chih-Wei CHANG
  • Publication number: 20240332076
    Abstract: Generally, examples are provided relating to conductive features that include a barrier layer, and to methods thereof. In an embodiment, a metal layer is deposited in an opening through a dielectric layer(s) to a source/drain region. The metal layer is along the source/drain region and along a sidewall of the dielectric layer(s) that at least partially defines the opening. The metal layer is nitrided, which includes performing a multiple plasma process that includes at least one directional-dependent plasma process. A portion of the metal layer remains un-nitrided by the multiple plasma process. A silicide region is formed, which includes reacting the un-nitrided portion of the metal layer with a portion of the source/drain region. A conductive material is disposed in the opening on the nitrided portions of the metal layer.
    Type: Application
    Filed: June 10, 2024
    Publication date: October 3, 2024
    Inventors: Wei-Yip Loh, Chih-Wei Chang, Hong-Mao Lee, Chun-Hsien Huang, Yu-Ming Huang, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Yu-Kai Chen, Yu-Wen Cheng
  • Publication number: 20240297228
    Abstract: Semiconductor structures and methods of forming the same are provided. A method of the present disclosure includes receiving a workpiece that includes a bottom source/drain feature over a substrate, a first dielectric layer over the bottom source/drain feature, a top source/drain feature over the first dielectric layer, and a second dielectric layer over the top source/drain feature, forming a frontside opening through the second dielectric layer to expose a portion of the top source/drain feature, selectively depositing a first silicide layer on the exposed portion of the top source/drain feature, forming a top metal fill layer over the first silicide layer to fill the frontside opening, forming a backside opening through the substrate to expose a portion of the bottom source/drain feature, selectively depositing a second silicide layer on the exposed portion of the bottom source/drain feature, and forming a bottom metal fill layer on the second silicide layer.
    Type: Application
    Filed: May 25, 2023
    Publication date: September 5, 2024
    Inventors: Wei-Yip Loh, Hong-Mao Lee, Harry Chien, Chih-Wei Chang
  • Patent number: 12046510
    Abstract: Generally, examples are provided relating to conductive features that include a barrier layer, and to methods thereof. In an embodiment, a metal layer is deposited in an opening through a dielectric layer(s) to a source/drain region. The metal layer is along the source/drain region and along a sidewall of the dielectric layer(s) that at least partially defines the opening. The metal layer is nitrided, which includes performing a multiple plasma process that includes at least one directional-dependent plasma process. A portion of the metal layer remains un-nitrided by the multiple plasma process. A silicide region is formed, which includes reacting the un-nitrided portion of the metal layer with a portion of the source/drain region. A conductive material is disposed in the opening on the nitrided portions of the metal layer.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yip Loh, Chih-Wei Chang, Hong-Mao Lee, Chun-Hsien Huang, Yu-Ming Huang, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Yu-Kai Chen, Yu-Wen Cheng
  • Patent number: 11932718
    Abstract: Exfoliated nanoplatelets functionalized with a non-polar moiety, such as an ethylene or propylene derived polymer, are useful for forming composites, films, and polymer blends.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: March 19, 2024
    Assignees: The Texas A&M University System, Formosa Plastics Corporation
    Inventors: Hung-Jue Sue, Joseph Baker, Mingzhen Zhao, Hong-Mao Wu, Wen-Hao Kang, Jen-Long Wu
  • Publication number: 20240048184
    Abstract: Implants include a single tapped coil antenna having a first section and a second section for wireless power transfer, data downlink and data uplink. A modulated wireless power transfer signal is received by the tapped coil antenna and used to provide electrical power. The modulation is detected to generate downlink data. A switch is used to charge a section of the tapped coil antenna by establish a current which is then be interrupted by opening the switch. The switching produces a high-amplitude pulsed magnetic field (PMF) for use in data uplink over a large distance between the implant and an external transceiver.
    Type: Application
    Filed: December 7, 2021
    Publication date: February 8, 2024
    Applicant: University of Pittsburgh – Of the Commonwealth System of Higher Education
    Inventors: Mingui Sun, Zhi-Hong Mao, Wenyan Jia, Tianfeng Wang, Qi Xu
  • Publication number: 20230411242
    Abstract: The present disclosure describes a buried conductive structure in a semiconductor substrate and a method for forming the structure. The structure includes an epitaxial region disposed on a substrate and adjacent to a nanostructured gate layer and a nanostructured channel layer, a first silicide layer disposed within a top portion of the epitaxial region, and a first conductive structure disposed on a top surface of the first silicide layer. The structure further includes a second silicide layer disposed within a bottom portion of the epitaxial region and a second conductive structure disposed on a bottom surface of the second silicide layer and traversing through the substrate, where the second conductive structure includes a first metal layer in contact with the second silicide layer and a second metal layer in contact with the first metal layer.
    Type: Application
    Filed: June 17, 2022
    Publication date: December 21, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kan-Ju LIN, Lin-Yu HUANG, Min-Hsuan LU, Wei-Yip LOH, Hong-Mao LEE, Harry CHIEN
  • Publication number: 20230411496
    Abstract: A semiconductor structure and method of forming a semiconductor structure are provided. In some embodiments, the method includes forming a gate structure over a substrate. An epitaxial source/drain region is formed adjacent to the gate structure. A dielectric layer is formed over the epitaxial source/drain region. An opening is formed, the opening extending through the dielectric layer and exposing the epitaxial source/drain region. Sidewalls of the opening are defined by the dielectric layer and a bottom of the opening is defined by the epitaxial source/drain region. A silicide layer is formed on the epitaxial source/drain region. A metal capping layer including tungsten, molybdenum, or a combination thereof is selectively formed on the silicide layer by a first deposition process. The opening is filled with a first conductive material in a bottom-up manner from the metal capping layer by a second deposition process different from the first deposition process.
    Type: Application
    Filed: May 23, 2022
    Publication date: December 21, 2023
    Inventors: Kan-Ju LIN, Chien CHANG, Chih-Shiun CHOU, Tai Min CHANG, Yi-Ning TAI, Hong-Mao LEE, Yan-Ming TSAI, Wei-Yip LOH, Harry CHIEN, Chih-Wei CHANG, Ming-Hsing TSAI, Lin-Yu HUANG
  • Publication number: 20230402278
    Abstract: A method of forming a semiconductor device includes following operations. A substrate is provided with a gate stack thereon, an epitaxial layer therein, and a dielectric layer aside the gate stack and over the epitaxial layer. An opening is formed through the dielectric layer, and the opening exposes the epitaxial layer. A metal silicon-germanide layer is formed on the epitaxial layer, wherein the metal silicon-germanide layer includes a metal having a melting point of about 1700° C. or higher. A connector is formed over the metal silicon-germanide layer in the opening.
    Type: Application
    Filed: June 12, 2022
    Publication date: December 14, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yan-Ming Tsai, Wei-Yip Loh, Harry CHIEN, Chih-Shiun Chou, Hong-Mao Lee, Chih-Wei Chang, Ming-Hsing Tsai
  • Publication number: 20230402366
    Abstract: A semiconductor device includes a substrate, a source/drain region disposed in the substrate, a silicide structure disposed on the source/drain region, a first dielectric layer disposed over the substrate, a conductive contact disposed in the first dielectric layer and over the silicide structure, a second dielectric layer disposed over the first dielectric layer, a via contact disposed in the second dielectric layer and connected to the conductive contact, and a first metal surrounding the via contact.
    Type: Application
    Filed: June 9, 2022
    Publication date: December 14, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shuen-Shin LIANG, Chia-Hung CHU, Po-Chin CHANG, Hsu-Kai CHANG, Kuan-Kan HU, Ken-Yu CHANG, Hung-Yi HUANG, Harry CHIEN, Wei-Yip LOH, Chun-I TSAI, Hong-Mao LEE, Sung-Li WANG, Pinyen LIN, Chuan-Hui SHEN
  • Publication number: 20230387316
    Abstract: A semiconductor device includes a source/drain portion, a metal silicide layer disposed over the source/drain portion, and a transition layer disposed between the source/drain portion and the metal silicide layer. The transition layer includes implantation elements, and an atomic concentration of the implantation elements in the transition layer is higher than that in each of the source/drain portion and the metal silicide layer so as to reduce a contact resistance between the source/drain portion and the metal silicide layer. Methods for manufacturing the semiconductor device are also disclosed.
    Type: Application
    Filed: May 26, 2022
    Publication date: November 30, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shuen-Shin LIANG, Min-Chiang CHUANG, Chia-Cheng CHEN, Chun-Hung WU, Liang-Yin CHEN, Sung-Li WANG, Pinyen LIN, Kuan-Kan HU, Jhih-Rong HUANG, Szu-Hsian LEE, Tsun-Jen CHAN, Cheng-Wei LIAN, Po-Chin CHANG, Chuan-Hui SHEN, Lin-Yu HUANG, Yuting CHENG, Yan-Ming TSAI, Hong-Mao LEE
  • Publication number: 20230386918
    Abstract: A semiconductor device is disclosed. The device includes a source/drain feature formed over a substrate. A dielectric layer formed over the source/drain feature. A contact trench formed through the dielectric layer to expose the source/drain feature. A titanium nitride (TiN) layer deposited in the contact trench and a cobalt layer deposited over the TiN layer in the contact trench.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 30, 2023
    Inventors: Chun-Hsien Huang, Hong-Mao Lee, Hsien-Lung Yang, Yu-Kai Chen, Wei-Jung Lin