Patents by Inventor Hong-Mao Lee

Hong-Mao Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200176382
    Abstract: A method for fabricating a semiconductor arrangement includes removing a portion of a first dielectric layer to form a first recess defined by sidewalls of the first dielectric layer, forming a first conductive layer in the first recess, removing a portion of the first conductive layer to form a second recess defined by the sidewalls of the first dielectric layer, forming a second conductive layer in the second recess, where the second conductive layer contacts the first conductive layer, forming a second dielectric layer over the second conductive layer, removing a portion of the second dielectric layer to form a third recess defined by sidewalls of the second dielectric layer, where the second conductive layer is exposed through the third recess, and forming a third conductive layer in the third recess, where the third conductive layer contacts the second conductive layer.
    Type: Application
    Filed: November 13, 2019
    Publication date: June 4, 2020
    Inventors: Pin-Wen Chen, Mei-Hui Fu, Hong-Mao Lee, Wei-jung Lin, Chih-Wei Chang
  • Publication number: 20200152763
    Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.
    Type: Application
    Filed: January 13, 2020
    Publication date: May 14, 2020
    Inventors: Yu-Wen Cheng, Cheng-Tung Lin, Chih-Wei Chang, Hong-Mao Lee, Ming-Hsing Tsai, Sheng-Hsuan Lin, Wei-Jung Lin, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Wei-Yip Loh, Ya-Yi Cheng
  • Publication number: 20200118935
    Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventors: Hong-Mao LEE, Huicheng CHANG, Chia-Han LAI, Chi-Hsuan NI, Cheng-Tung LIN, Huang-Yi HUANG, Chi-Yuan CHEN, Li-Ting WANG, Teng-Chun TSAI, Wei-Jung LIN
  • Publication number: 20200111739
    Abstract: A method for forming a semiconductor contact structure is provided. The method includes depositing a dielectric layer over a substrate. The method also includes etching the dielectric layer to expose a sidewall of the dielectric layer and a top surface of the substrate. In addition, the method includes forming a silicide region in the substrate. The method also includes applying a plasma treatment to the sidewall of the dielectric layer and the top surface of the substrate to form a nitridation region adjacent to a periphery of the silicide region. The method further includes depositing an adhesion layer on the dielectric layer and the silicide region.
    Type: Application
    Filed: December 9, 2019
    Publication date: April 9, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Wen CHENG, Wei-Yip LOH, Yu-Hsiang LIAO, Sheng-Hsuan LIN, Hong-Mao LEE, Chun-I TSAI, Ken-Yu CHANG, Wei-Jung LIN, Chih-Wei CHANG, Ming-Hsing TSAI
  • Patent number: 10535748
    Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Wen Cheng, Cheng-Tung Lin, Chih-Wei Chang, Hong-Mao Lee, Ming-Hsing Tsai, Sheng-Hsuan Lin, Wei-Jung Lin, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Wei-Yip Loh, Ya-Yi Cheng
  • Publication number: 20200013674
    Abstract: A semiconductor device is disclosed. The device includes a source/drain feature formed over a substrate. A dielectric layer formed over the source/drain feature. A contact trench formed through the dielectric layer to expose the source/drain feature. A titanium nitride (TiN) layer deposited in the contact trench and a cobalt layer deposited over the TiN layer in the contact trench.
    Type: Application
    Filed: September 16, 2019
    Publication date: January 9, 2020
    Inventors: Chun-Hsien Huang, Hong-Mao Lee, Hsien-Lung Yang, Yu-Kai Chen, Wei-Jung Lin
  • Patent number: 10510664
    Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hong-Mao Lee, Huicheng Chang, Chia-Han Lai, Chi-Hsuan Ni, Cheng-Tung Lin, Huang-Yi Huang, Chi-Yuan Chen, Li-Ting Wang, Teng-Chun Tsai, Wei-Jung Lin
  • Patent number: 10504834
    Abstract: A semiconductor device and method of forming the same that includes forming a dielectric layer over a substrate and patterning a contact region in the dielectric layer, the contact region having side portions and a bottom portion that exposes the substrate. The method can also include forming a dielectric barrier layer in the contact region to cover the side portions and the bottom portion, and etching the dielectric barrier layer to expose the substrate. Subsequently, a conductive layer can be formed to cover the side portions and the bottom portion of the contact region and the conductive layer can be annealed to form a silicide region in the substrate beneath the bottom portion of the contact region, and the conductive layer can then be selectively removed on the side portions of the contact region.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Wen Cheng, Wei-Yip Loh, Yu-Hsiang Liao, Sheng-Hsuan Lin, Hong-Mao Lee, Chun-I Tsai, Ken-Yu Chang, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
  • Patent number: 10418279
    Abstract: A semiconductor device is disclosed. The device includes a source/drain feature formed over a substrate. A dielectric layer formed over the source/drain feature. A contact trench formed through the dielectric layer to expose the source/drain feature. A titanium nitride (TiN) layer deposited in the contact trench and a cobalt layer deposited over the TiN layer in the contact trench.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: September 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Hsien Huang, Hong-Mao Lee, Hsien-Lung Yang, Yu-Kai Chen, Wei-Jung Lin
  • Publication number: 20190273042
    Abstract: A semiconductor device and method of forming the same that includes forming a dielectric layer over a substrate and patterning a contact region in the dielectric layer, the contact region having side portions and a bottom portion that exposes the substrate. The method can also include forming a dielectric barrier layer in the contact region to cover the side portions and the bottom portion, and etching the dielectric barrier layer to expose the substrate. Subsequently, a conductive layer can be formed to cover the side portions and the bottom portion of the contact region and the conductive layer can be annealed to form a silicide region in the substrate beneath the bottom portion of the contact region, and the conductive layer can then be selectively removed on the side portions of the contact region.
    Type: Application
    Filed: March 1, 2018
    Publication date: September 5, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Wen Cheng, Wei-Yip Loh, Yu-Hsiang Liao, Sheng-Hsuan Lin, Hong-Mao Lee, Chun-I Tsai, Ken-Yu Chang, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
  • Publication number: 20190273023
    Abstract: Generally, examples are provided relating to conductive features that include a barrier layer, and to methods thereof. In an embodiment, a metal layer is deposited in an opening through a dielectric layer(s) to a source/drain region. The metal layer is along the source/drain region and along a sidewall of the dielectric layer(s) that at least partially defines the opening. The metal layer is nitrided, which includes performing a multiple plasma process that includes at least one directional-dependent plasma process. A portion of the metal layer remains un-nitrided by the multiple plasma process. A silicide region is formed, which includes reacting the un-nitrided portion of the metal layer with a portion of the source/drain region. A conductive material is disposed in the opening on the nitrided portions of the metal layer.
    Type: Application
    Filed: March 1, 2018
    Publication date: September 5, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Yip LOH, Chih-Wei CHANG, Hong-Mao LEE, Chun-Hsien HUANG, Yu-Ming HUANG, Yan-Ming TSAI, Yu-Shiuan WANG, Hung-Hsu CHEN, Yu-Kai CHEN, Yu-Wen CHENG
  • Publication number: 20190273147
    Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.
    Type: Application
    Filed: March 1, 2018
    Publication date: September 5, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Wen CHENG, Cheng-Tung LIN, Chih-Wei CHANG, Hong-Mao LEE, Ming-Hsing TSAI, Sheng-Hsuan LIN, Wei-Jung LIN, Yan-Ming TSAI, Yu-Shiuan WANG, Hung-Hsu CHEN, Wei-Yip LOH, Ya-Yi CHENG
  • Patent number: 10283359
    Abstract: Systems and methods are provided for contact formation. A semiconductor structure is provided. The semiconductor structure includes an opening formed by a bottom surface and one or more side surfaces. A first conductive material is formed on the bottom surface and the one or more side surfaces to partially fill the opening, the first conductive material including a top portion and a bottom portion. Ion implantation is formed on the first conductive material, the top portion of the first conductive material being associated with a first ion density, the bottom portion of the first conductive material being associated with a second ion density lower than the first ion density. At least part of the top portion of the first conductive material is removed. A second conductive material is formed to fill the opening.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: May 7, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chi-Yuan Chen, Li-Ting Wang, Teng-Chun Tsai, Chun-I Tsai, Wei-Jung Lin, Huang-Yi Huang, Cheng-Tung Lin, Hong-Mao Lee
  • Patent number: 10157995
    Abstract: A method includes forming a gate stack over a semiconductor region, depositing an impurity layer over the semiconductor region, and depositing a metal layer over the impurity layer. An annealing is then performed, wherein the elements in the impurity layer are diffused into a portion of the semiconductor region by the annealing to form a source/drain region, and wherein the metal layer reacts with a surface layer of the portion of the semiconductor region to form a source/drain silicide region over the source/drain region.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Ting Wang, Teng-Chun Tsai, Chun-Hsiung Lin, Cheng-Tung Lin, Chi-Yuan Chen, Hong-Mao Lee, Huicheng Chang
  • Publication number: 20170345765
    Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.
    Type: Application
    Filed: August 14, 2017
    Publication date: November 30, 2017
    Inventors: Hong-Mao Lee, Huicheng Chang, Chia-Han Lai, Chi-Hsuan Ni, Cheng-Tung Lin, Huang-Yi Huang, Chi-Yuan Chen, Li-Ting Wang, Teng-Chun Tsai, Wei-Jung Lin
  • Publication number: 20170287779
    Abstract: A semiconductor device is disclosed. The device includes a source/drain feature formed over a substrate. A dielectric layer formed over the source/drain feature. A contact trench formed through the dielectric layer to expose the source/drain feature. A titanium nitride (TiN) layer deposited in the contact trench and a cobalt layer deposited over the TiN layer in the contact trench.
    Type: Application
    Filed: June 20, 2017
    Publication date: October 5, 2017
    Inventors: Chun-Hsien Huang, Hong-Mao Lee, Hsien-Lung Yang, Yu-Kai Chen, Wei-Jung Lin
  • Patent number: 9735107
    Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: August 15, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hong-Mao Lee, Huicheng Chang, Chia-Han Lai, Chi-Hsuan Ni, Cheng-Tung Lin, Huang-Yi Huang, Chi-Yuan Chen, Li-Ting Wang, Teng-Chun Tsai, Wei-Jung Lin
  • Publication number: 20170221710
    Abstract: Systems and methods are provided for contact formation. A semiconductor structure is provided. The semiconductor structure includes an opening formed by a bottom surface and one or more side surfaces. A first conductive material is formed on the bottom surface and the one or more side surfaces to partially fill the opening, the first conductive material including a top portion and a bottom portion. Ion implantation is formed on the first conductive material, the top portion of the first conductive material being associated with a first ion density, the bottom portion of the first conductive material being associated with a second ion density lower than the first ion density. At least part of the top portion of the first conductive material is removed. A second conductive material is formed to fill the opening.
    Type: Application
    Filed: April 17, 2017
    Publication date: August 3, 2017
    Inventors: Chi-Yuan Chen, Li-Ting Wang, Teng-Chun Tsai, Chun-I Tsai, Wei-Jung Lin, Huang-Yi Huang, Cheng-Tung Lin, Hong-Mao Lee
  • Patent number: 9711402
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a source/drain feature over a substrate, forming a dielectric layer over the source/drain feature, forming a contact trench through the dielectric layer to expose the source/drain feature, depositing a titanium nitride (TiN) layer by a first atomic layer deposition (ALD) process in the contact trench and depositing a cobalt layer over the TiN layer in the contact trench.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: July 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hsien Huang, Hong-Mao Lee, Hsien-Lung Yang, Yu-Kai Chen, Wei-Jung Lin
  • Patent number: 9624576
    Abstract: Systems and methods are provided for contact formation. A semiconductor structure is provided. The semiconductor structure includes an opening formed by a bottom surface and one or more side surfaces. A first conductive material is formed on the bottom surface and the one or more side surfaces to partially fill the opening, the first conductive material including a top portion and a bottom portion. Ion implantation is formed on the first conductive material, the top portion of the first conductive material being associated with a first ion density, the bottom portion of the first conductive material being associated with a second ion density lower than the first ion density. At least part of the top portion of the first conductive material is removed. A second conductive material is formed to fill the opening.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chi-Yuan Chen, Li-Ting Wang, Teng-Chun Tsai, Chun-I Tsai, Wei-Jung Lin, Huang-Yi Huang, Cheng-Tung Lin, Hong-Mao Lee