Patents by Inventor Hong-men Su
Hong-men Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10120688Abstract: A data processing system includes a control register, a program counter and a controller. The control register is used to store a level status of an execution flow and at least one return address. When the controller reads a block call instruction while a level status of the execution flow has an initial value, the controller stores a return address of the block call instruction in the control register, increments a value of the level status, and redirects the execution flow to a target address indicated by the block call instruction. When the controller reads a block return instruction and the value of the level status is not equal to the initial value, the controller decrements the value of the level status. If the value of the level status becomes equal to the initial value, the controller redirects the execution flow to the return address.Type: GrantFiled: November 15, 2016Date of Patent: November 6, 2018Assignee: Andes Technology CorporationInventors: Jen-Chih Tseng, Hong-Men Su, Chuan-Hua Chang
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Publication number: 20180136934Abstract: A data processing system includes a control register, a program counter and a controller. The control register is used to store a level status of an execution flow and at least one return address. When the controller reads a block call instruction while a level status of the execution flow has an initial value, the controller stores a return address of the block call instruction in the control register, increments a value of the level status, and redirects the execution flow to a target address indicated by the block call instruction. When the controller reads a block return instruction and the value of the level status is not equal to the initial value, the controller decrements the value of the level status. If the value of the level status becomes equal to the initial value, the controller redirects the execution flow to the return address.Type: ApplicationFiled: November 15, 2016Publication date: May 17, 2018Inventors: Jen-Chih Tseng, Hong-Men Su, Chuan-Hua Chang
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Patent number: 9672041Abstract: A method for compressing instruction is provided, which includes the following steps. Analyze a program code to be executed by a processor to find one or more instruction groups in the program code according to a preset condition. Each of the instruction groups includes one or more instructions in sequential order. Sort the one or more instruction groups according to a cost function of each of the one or more instruction groups. Put the first X of the sorted one or more instruction groups into an instruction table. X is a value determined according to the cost function. Replace each of the one or more instruction groups in the program code that are put into the instruction table with a corresponding execution-on-instruction-table (EIT) instruction. The EIT instruction has a parameter referring to the corresponding instruction group in the instruction table.Type: GrantFiled: August 1, 2013Date of Patent: June 6, 2017Assignee: ANDES TECHNOLOGY CORPORATIONInventors: Wei-Hao Chiao, Hong-Men Su, Haw-Luen Tsai
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Patent number: 8972705Abstract: A constant data accessing system having a constant pool comprises a computer processor having a constant pool base register, a compiler having a constant pool handler, and an instruction set module having a constant pool instruction set unit. The constant pool base register is configured to store a value of constant pool base address of one or a plurality of subroutines which have constants to be accessed.Type: GrantFiled: November 16, 2011Date of Patent: March 3, 2015Assignee: Andes Technology CorporationInventors: Wei-Hao Chiao, Haw-Luen Tsai, Chen-Wei Chang, Hong-Men Su
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Publication number: 20150039863Abstract: A method for compressing instruction is provided, which includes the following steps. Analyze a program code to be executed by a processor to find one or more instruction groups in the program code according to a preset condition. Each of the instruction groups includes one or more instructions in sequential order. Sort the one or more instruction groups according to a cost function of each of the one or more instruction groups. Put the first X of the sorted one or more instruction groups into an instruction table. X is a value determined according to the cost function. Replace each of the one or more instruction groups in the program code that are put into the instruction table with a corresponding execution-on-instruction-table (EIT) instruction. The EIT instruction has a parameter referring to the corresponding instruction group in the instruction table.Type: ApplicationFiled: August 1, 2013Publication date: February 5, 2015Applicant: ANDES TECHNOLOGY CORPORATIONInventors: Wei-Hao Chiao, Hong-Men Su, Haw-Luen Tsai
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Patent number: 8756605Abstract: An apparatus and method for scheduling execution of multiple threads on a shared processor resource is described in connection with a multithreaded multiprocessor chip. Using a thread selection policy that switches between available threads every cycle to give priority to the least recently executed or scheduled threads, different threads are able to operate in a way that ensures no deadlocks or livelocks while maximizing aggregate performance and fairness between threads. Prioritization is accomplished by monitoring and sorting thread status information for each thread, including speculative states in which a thread may be speculatively scheduled, thereby improving usage of the execution pipeline by switching a thread in with a lower priority.Type: GrantFiled: December 17, 2004Date of Patent: June 17, 2014Assignee: Oracle America, Inc.Inventors: Kathirgamar Aingaran, Hong-Men Su
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Publication number: 20130124836Abstract: A constant data accessing system having a constant pool comprises a computer processor having a constant pool base register, a compiler having a constant pool handler, and an instruction set module having a constant pool instruction set unit. The constant pool base register is configured to store a value of constant pool base address of one or a plurality of subroutines which have constants to be accessed.Type: ApplicationFiled: November 16, 2011Publication date: May 16, 2013Applicant: ANDES TECHNOLOGY CORPORATIONInventors: WEI-HAO CHIAO, HAW-LUEN TSAI, CHEN-WEI CHANG, HONG-MEN SU
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Patent number: 8171188Abstract: To handle boundary conditions efficiently during bitstream extraction, a predetermined number of bits are extracted from the bitstream register starting from a most significant bit of the bitstream register when an underflow flag is set. The predetermined number equals a predetermined extraction width minus a previous starting position. The bits are stored in a lowest part of a destination register, and the underflow flag is cleared.Type: GrantFiled: November 16, 2008Date of Patent: May 1, 2012Assignee: Andes Technology CorporationInventors: Chuan-Hua Chang, Hong-Men Su
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Patent number: 7971043Abstract: An electronic system includes a pipeline having a first number of pipeline stages coupled in series, a pipeline control unit, and a logic engine, wherein each pipeline stage in the pipeline is for outputting data to a next pipeline stage at each cycle of a clock signal. The pipeline control unit is for changing the first number of pipeline stages in the pipeline to a second number of pipeline stages. The logic engine is for performing operations of the electronic system in a first mode by utilizing the pipeline having the first number of pipeline stages and for performing operations of the electronic system in a second mode by utilizing the pipeline having the second number of pipeline stages. A frequency control unit and a voltage control unit, coupled to the pipeline and the logic engine, respectively adjust the frequency and voltage of the electronic system accordingly.Type: GrantFiled: November 22, 2007Date of Patent: June 28, 2011Assignee: Andes Technology CorporationInventors: Li-Hung Chang, Hong-Men Su
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Patent number: 7934073Abstract: A method for performing a jump and translation state change procedure at the same time is disclosed. The method includes: carrying out a series of instruction processing in a first function in a first translation state; and executing a jump instruction which jumps to a target address in a second function and initiates and completes a translation state change to a second translation state at the same time; wherein an address of a next instruction after the jump instruction is stored as a return address in a first register.Type: GrantFiled: March 14, 2007Date of Patent: April 26, 2011Assignee: Andes Technology CorporationInventors: Chuan-Hua Chang, Hong-Men Su
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Patent number: 7822999Abstract: A computer system and a method for controlling a processor thereof are provided. A processor management unit (PMU) is programmed by the processor itself or by another processor according to a change of the operating condition of the processor. Then, a notification signal is sent to the PMU by the processor when the processor is entering a standby mode. Upon receiving the notification signal, the PMU adjusts the operating condition of the processor according to the change. Finally, a completion signal is sent by the PMU to the processor after the change of the operating condition of the processor is stabilized. Therefore, the unpredictable behavior caused by premature awakening of the processor during the adjustment of the operating condition can be avoided.Type: GrantFiled: June 4, 2007Date of Patent: October 26, 2010Assignee: Andes Technology CorporationInventors: Li-Hung Chang, Hong-Men Su, Chuan-Hua Chang
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Publication number: 20100211591Abstract: An exemplary string processing method for specific byte string processing with word-related instructions includes: loading a plurality of first predetermined strings; comparing a specific string with the loaded first predetermined strings simultaneously, thereby generating a plurality of comparison results corresponding to the specific string; and generating a string processing result according to the comparison results. A string processing apparatus uses the string processing method.Type: ApplicationFiled: February 16, 2009Publication date: August 19, 2010Inventors: Chuan-Hua Chang, Chi-Chang Lai, Hong-Men Su
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Publication number: 20100124308Abstract: To handle boundary conditions efficiently during bitstream extraction, a predetermined number of bits are extracted from the bitstream register starting from a most significant bit of the bitstream register when an underflow flag is set. The predetermined number equals a predetermined extraction width minus a previous starting position. The bits are stored in a lowest part of a destination register, and the underflow flag is cleared.Type: ApplicationFiled: November 16, 2008Publication date: May 20, 2010Inventors: Chuan-Hua Chang, Hong-Men Su
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Patent number: 7627743Abstract: A multi-word transfer instruction, a memory transfer method using the multi-word transfer instruction and a circuit implementation for transferring multiple words between a memory subsystem and a processor register file are provided. The multi-word transfer instruction specifies an access type (load or store), a consecutive register group, a selection mask and a base register for the starting address of the corresponding memory locations. Therefore, the total number of words accessed by this instruction is equal to the number of registers specified in the consecutive register group along with the number of the registers specified by the selection mask. Besides, additional information, such as an address update mode, an order mode and a modification mode, may be further specified in the multi-word transfer instruction.Type: GrantFiled: January 12, 2007Date of Patent: December 1, 2009Assignee: Andes Technology CorporationInventors: Hong-Men Su, Chuan-Hua Chang, Jen-Chih Tseng
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Publication number: 20090138674Abstract: An electronic system includes a pipeline having a first number of pipeline stages coupled in series, a pipeline control unit, and a logic engine, wherein each pipeline stage in the pipeline is for outputting data to a next pipeline stage at each cycle of a clock signal. The pipeline control unit is for changing the first number of pipeline stages in the pipeline to a second number of pipeline stages. The logic engine is for performing operations of the electronic system in a first mode by utilizing the pipeline having the first number of pipeline stages and for performing operations of the electronic system in a second mode by utilizing the pipeline having the second number of pipeline stages. A frequency control unit and a voltage control unit, coupled to the pipeline and the logic engine, respectively adjust the frequency and voltage of the electronic system accordingly.Type: ApplicationFiled: November 22, 2007Publication date: May 28, 2009Inventors: Li-Hung Chang, Hong-Men Su
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Patent number: 7519778Abstract: A system and a method for cache coherence are provided. The system includes a memory apparatus, a detector, a plurality of access-consumers and a plurality of pass-gates. At least one of the access-consumers is a processor having a cache. When the processor replaces the first data in cache with the second data read from the memory apparatus, the process issues the read second data request first, followed by the write-back first data request. The detector provides a detecting signal when the processor issues the read second data request and cancels the provided detecting signal when the processor issues the write-back first data request. Each pass-gate decides whether to pass the third access request outputting from each corresponding access-consumer and transmit it to the memory apparatus according to the detecting signal respectively.Type: GrantFiled: August 10, 2005Date of Patent: April 14, 2009Assignee: Faraday Technology Corp.Inventors: Hong-Men Su, Yung-Chung Liu, Chih-Yung Chiu, Chung-Hui Chen
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Publication number: 20080301480Abstract: A computer system and a method for controlling a processor thereof are provided. A processor management unit (PMU) is programmed by the processor itself or by another processor according to a change of the operating condition of the processor. Then, a notification signal is sent to the PMU by the processor when the processor is entering a standby mode. Upon receiving the notification signal, the PMU adjusts the operating condition of the processor according to the change. Finally, a completion signal is sent by the PMU to the processor after the change of the operating condition of the processor is stabilized. Therefore, the unpredictable behavior caused by premature awakening of the processor during the adjustment of the operating condition can be avoided.Type: ApplicationFiled: June 4, 2007Publication date: December 4, 2008Applicant: ANDES TECHNOLOGY CORPORATIONInventors: Li-Hung Chang, Hong-Men Su, Chuan-Hua Chang
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Publication number: 20080229054Abstract: A method for performing a jump and translation state change procedure at the same time is disclosed. The method includes: carrying out a series of instruction processing in a first function in a first translation state; and executing a jump instruction which jumps to a target address in a second function and initiates and completes a translation state change to a second translation state at the same time; wherein an address of a next instruction after the jump instruction is stored as a return address in a first register.Type: ApplicationFiled: March 14, 2007Publication date: September 18, 2008Inventors: Chuan-Hua Chang, Hong-Men Su
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Publication number: 20080172550Abstract: A multi-word transfer instruction, a memory transfer method using the multi-word transfer instruction and a circuit implementation for transferring multiple words between a memory subsystem and a processor register file are provided. The multi-word transfer instruction specifies an access type (load or store), a consecutive register group, a selection mask and a base register for the starting address of the corresponding memory locations. Therefore, the total number of words accessed by this instruction is equal to the number of registers specified in the consecutive register group along with the number of the registers specified by the selection mask. Besides, additional information, such as an address update mode, an order mode and a modification mode, may be further specified in the multi-word transfer instruction.Type: ApplicationFiled: January 12, 2007Publication date: July 17, 2008Applicant: ANDES TECHNOLOGY CORPORATIONInventors: Hong-Men Su, Chuan-Hua Chang, Jen-Chih Tseng
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Publication number: 20080140986Abstract: A method is disclosed for accessing a target register of a plurality of registers. The method includes: receiving an instruction containing a register index field; and mapping the register index field to the target register access index for accessing the target register. A data accessing apparatus corresponding to this method is also disclosed.Type: ApplicationFiled: December 8, 2006Publication date: June 12, 2008Inventors: Chuan-Hua Chang, Hong-Men Su, Jen-Chih Tseng