Abstract: A sense amplifier circuit for use in a semiconductor memory device has complemented logic states at opposite sides of the latch circuit in the sense amplifier circuit determinate all the time in operation. The sense amplifier circuit takes advantage of a current mirror circuit for ascending or descending a voltage level at the gate of a transistor by charge accumulation or charge dissipation, which turns on or off the transistor so as to control the logic states at opposite sides of the latch circuit in the sense amplifier circuit.

Abstract: A sense amplifier circuit for use in a semiconductor memory device has complemented logic states at opposite sides of the latch circuit in the sense amplifier circuit determinate all the time in operation. The sense amplifier circuit takes advantage of a current mirror circuit for ascending or descending a voltage level at the gate of a transistor by charge accumulation or charge dissipation, which turns on or off the transistor so as to control the logic states at opposite sides of the latch circuit in the sense amplifier circuit.

Abstract: A sensing amplifier comprising a program cell current sensing circuit, an erase cell current sensing circuit and a latch circuit is provided. Each of the program and erase cell current sensing circuits further comprises a plurality of program/erase memory cells, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth PMOS transistor. Wherein, one of the drain/source of the first NMOS transistor is electrically coupled to both the program/erase memory cells and a gate of the third NMOS transistor to form a node. In addition, one of the drain/source of the third NMOS transistor is coupled to the latch circuit. Moreover, the program/erase memory cell provides a program/erase current to the first NMOS transistor. The latch circuit will be driven once the amount of the electric charges accumulated at the node caused by the program/erase current overcomes a threshold voltage of the third NMOS transistor.

Abstract: A voltage selective circuit of a power source having a first voltage and a second voltage of the present invention includes a selective switch module, a high voltage bias module, a level shift module and a high voltage selective module. The selective switch module includes two first transistors. A power supply is selected from either the first voltage or the second voltage to output to integrated circuits. The high voltage bias module selects a higher voltage from the power supply and the power source of the first/second voltage to output to wells of the two first transistors. The level shift module includes two level shifters. The high voltage selective module selects a higher voltage from the first voltage and the second voltage as internal power to supply to the level shift module.

Abstract: A sensing amplifier comprising a program cell current sensing circuit, an erase cell current sensing circuit and a latch circuit is provided. Each of the program and erase cell current sensing circuits further comprises a plurality of program/erase memory cells, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth PMOS transistor. Wherein, one of the drain/source of the first NMOS transistor is electrically coupled to both the program/erase memory cells and a gate of the third NMOS transistor to form a node. In addition, one of the drain/source of the third NMOS transistor is coupled to the latch circuit. Moreover, the program/erase memory cell provides a program/erase current to the first NMOS transistor. The latch circuit will be driven once the amount of the electric charges accumulated at the node caused by the program/erase current overcomes a threshold voltage of the third NMOS transistor.

Abstract: A boost circuit comprising a first level shifter and a switch circuit is provided. The first level shifter outputs either an output voltage of the boost circuit or a first bias voltage according to a boost control signal. The switch circuit determines whether to transmit a second bias voltage to an output terminal of the boost circuit according to the output of the first level shifter. The present invention further comprises a capacitance equivalent circuit and a second level shifter. The capacitance equivalent circuit comprises a first terminal and a second terminal, and the first terminal is electrically coupled to the output terminal of the boost circuit. Similarly, the second level shifter outputs a third bias voltage or the first bias voltage to the second terminal of the capacitance equivalent circuit. In addition, the first bias voltage is smaller than the second bias voltage and the third bias voltage.

Abstract: A power supply voltage switch circuit for selecting a power supply voltage of an integrated circuit according to a first control signal. The power supply voltage switch circuit contains a high voltage selecting module for generating an output voltage according to the higher of a first and a second voltages; a level shifting module electrically connected to the high voltage selecting module to receive the output voltage as power supply, for performing level shifting to a first control signal according to the output voltage; and a selecting switch module electrically connected to the level shifting module for selectively outputting the first or the second voltage as the power supply voltage of the integrated circuit according to the level-shifted first control signal.

Abstract: An erasable programmable non-volatile memory cell encompasses an ion well; a first select transistor including a select gate, source/drain formed in the ion well, and a channel region formed between its source and drain; a first floating gate transistor having a drain, a source coupled to the drain of the first select transistor, a first floating gate channel region formed between its drain and source, and a common floating gate overlying the floating gate channel region; a second select transistor including a select gate, source/drain formed in the ion well, and a channel region formed between its source and drain; and a second floating gate transistor having a drain, a source coupled to the drain of the second select transistor, a second floating gate channel region formed between its drain and source, and the common floating gate overlying the second floating gate channel region.

Abstract: A voltage selective circuit of a power source having a first voltage and a second voltage of the present invention includes a selective switch module, a high voltage bias module, a level shift module and a high voltage selective module. The selective switch module includes two first transistors. A power supply is selected from either the first voltage or the second voltage to output to integrated circuits. The high voltage bias module selects a higher voltage from the power supply and the power source of the first/second voltage to output to wells of the two first transistors. The level shift module includes two level shifters. The high voltage selective module selects a higher voltage from the first voltage and the second voltage as internal power to supply to the level shift module.

Abstract: An erasable programmable non-volatile memory cell encompasses an ion well; a first select transistor including a select gate, source/drain formed in the ion well, and a channel region formed between its source and drain; a first floating gate transistor having a drain, a source coupled to the drain of the first select transistor, a first floating gate channel region formed between its drain and source, and a common floating gate overlying the floating gate channel region; a second select transistor including a select gate, source/drain formed in the ion well, and a channel region formed between its source and drain; and a second floating gate transistor having a drain, a source coupled to the drain of the second select transistor, a second floating gate channel region formed between its drain and source, and the common floating gate overlying the second floating gate channel region.

Abstract: A power supply voltage switch circuit for selecting a power supply voltage of an integrated circuit according to a first control signal. The power supply voltage switch circuit contains a high voltage selecting module for generating an output voltage according to the higher of a first and a second voltages; a level shifting module electrically connected to the high voltage selecting module to receive the output voltage as power supply, for performing level shifting to a first control signal according to the output voltage; and a selecting switch module electrically connected to the level shifting module for selectively outputting the first or the second voltage as the power supply voltage of the integrated circuit according to the level-shifted first control signal.

Abstract: A memory including a plurality of memory cells, a sensing load, a reference load, a control circuit and a comparator. Each of the memory cells can store a bit data and provide a driving current according to the bit data. The sensing load is driven by the driving current and a driving voltage to generate a sensing voltage, and the reference load is driven by the driving voltage to generate a reference voltage. The control circuit can control the driving voltage to drive the sensing load or the reference load such that the sensing voltage or the reference voltage is kept constant while the driving current changes. The comparator is for comparing the sensing voltage with the reference voltage and therefore determining the bit data stored in the memory cell that provides the driving current.

Abstract: A memory including a plurality of memory cells, a sensing load, a reference load, a control circuit and a comparator. Each of the memory cells can store a bit data and provide a driving current according to the bit data. The sensing load is driven by the driving current and a driving voltage to generate a sensing voltage, and the reference load is driven by the driving voltage to generate a reference voltage. The control circuit can control the driving voltage to drive the sensing load or the reference load such that the sensing voltage or the reference voltage is kept constant while the driving current changes. The comparator is for comparing the sensing voltage with the reference voltage and therefore determining the bit data stored in the memory cell that provides the driving current.

Abstract: A charge pumping circuit for reducing body effect and boosting charging performance. Two of pull-up circuits are employed so that the source terminal of the NMOS transistor in each charging circuit stage is connected to the drain terminal of a corresponding NMOS transistor in the next stage. Furthermore, the gate terminal of the NMOS transistor of a first group pull-up circuit is connected to the source terminal of the NMOS transistor of a second group pull-up circuit. Similarly, the gate terminal of the NMOS transistor of the second group pull-up circuit is connected to the source terminal of the NMOS transistor of the first group pull-up circuit. In addition, a CMOS circuit may be employed to control the NMOS transistor in each stage more efficiently.