Patents by Inventor Hong Pyo Heo

Hong Pyo Heo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9276098
    Abstract: According to example embodiments, a high electron mobility transistor (HEMT) includes a first semiconductor layer on a substrate and a second semiconductor layer on the first semiconductor layer. The first and second semiconductor layers define a recessed region. A semiconductor doped layer is in the recessed region of first and second semiconductor layers. A 2-dimensional electron gas (2DEG) region is at a portion of the first semiconductor layer adjacent to both sides of the semiconductor doped layer.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: March 1, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hong-Pyo Heo
  • Publication number: 20150054035
    Abstract: According to example embodiments, a high electron mobility transistor (HEMT) includes a first semiconductor layer on a substrate and a second semiconductor layer on the first semiconductor layer. The first and second semiconductor layers define a recessed region. A semiconductor doped layer is in the recessed region of first and second semiconductor layers. A 2-dimensional electron gas (2DEG) region is at a portion of the first semiconductor layer adjacent to both sides of the semiconductor doped layer.
    Type: Application
    Filed: November 4, 2014
    Publication date: February 26, 2015
    Inventor: Hong-Pyo HEO
  • Patent number: 8912572
    Abstract: According to example embodiments, a high electron mobility transistor (HEMT) includes a first semiconductor layer on a substrate and a second semiconductor layer on the first semiconductor layer. The first and second semiconductor layers define a recessed region. A semiconductor doped layer is in the recessed region of first and second semiconductor layers. A 2-dimensional electron gas (2DEG) region is at a portion of the first semiconductor layer adjacent to both sides of the semiconductor doped layer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hong-Pyo Heo
  • Publication number: 20140147973
    Abstract: A method of packaging power devices at a wafer level is disclosed. The method includes preparing a wafer having a plurality of nitride power devices thereon, each of the plurality of nitride power devices having a plurality of electrodes thereon; forming a polymer layer on the plurality of nitride power devices; exposing each of the electrodes from the polymer layer; forming a solder bump on the exposed electrodes; forming a molding layer covering the solder bump on the polymer layer; and removing the wafer and exposing the solder bump.
    Type: Application
    Filed: July 10, 2013
    Publication date: May 29, 2014
    Inventors: Hyuk-soon CHOI, Hong-Pyo HEO, Jong-seob KIM, Jai-kwang SHIN, Jae-joon OH, In-jun HWANG
  • Publication number: 20140077388
    Abstract: A semiconductor device includes a device chip coupled to an electrode chip. The device chip includes a first device electrode on a first substrate, and the electrode chip includes a first pad electrode extending at least partially through a second substrate. The first pad electrode is electrically connected to the first device electrode and includes spaced conductive sections which serve as a heat dissipating structure to transfer heat received from the device chip and the electrode chip. A method for making a semiconductor device includes using the substrate of the electrode chip as a support during thinning the substrate of the device chip.
    Type: Application
    Filed: January 25, 2013
    Publication date: March 20, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-Pyo HEO, Young-soo KWON, Jai-kwang SHIN, Young-tek OH, Hyung-su JEONG
  • Publication number: 20140077267
    Abstract: According to example embodiments, a high electron mobility transistor (HEMT) includes a first semiconductor layer on a substrate and a second semiconductor layer on the first semiconductor layer. The first and second semiconductor layers define a recessed region. A semiconductor doped layer is in the recessed region of first and second semiconductor layers. A 2-dimensional electron gas (2DEG) region is at a portion of the first semiconductor layer adjacent to both sides of the semiconductor doped layer.
    Type: Application
    Filed: March 15, 2013
    Publication date: March 20, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hong-Pyo HEO
  • Patent number: 8120096
    Abstract: A power semiconductor device capable of transmitting gate signals in all directions (e.g., up-/down-ward/right-/left-ward) on a plane and a method of manufacturing the same. The power semiconductor device includes first conductive regions, formed to a predetermined depth in a surface of a conductive low concentration epitaxial layer. The first conductive regions include linear first conductive layers spaced from each other and linear second conductive layers spaced from each other. Second conductive regions are formed to a smaller width and depth than the first and second conductive layers to form channels in the first and second conductive layers. A gate oxide layer formed on a surface of the epitaxial layer defines first windows having a smaller width than the first conductive layers and second windows having a smaller width than the second conductive layers. A gate polysilicon layer is formed on the gate oxide layer.
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: February 21, 2012
    Assignee: KEC Corporation
    Inventors: Hong Pyo Heo, Keum Hwang
  • Publication number: 20090224310
    Abstract: A power semiconductor device capable of transmitting gate signals in all directions (e.g., up-/down-ward/right-/left-ward) on a plane and a method of manufacturing the same. The power semiconductor device includes first conductive regions, formed to a predetermined depth in a surface of a conductive low concentration epitaxial layer. The first conductive regions include linear first conductive layers spaced from each other and linear second conductive layers spaced from each other. Second conductive regions are formed to a smaller width and depth than the first and second conductive layers to form channels in the first and second conductive layers. A gate oxide layer formed on a surface of the epitaxial layer defines first windows having a smaller width than the first conductive layers and second windows having a smaller width than the second conductive layers. A gate polysilicon layer is formed on the gate oxide layer.
    Type: Application
    Filed: March 3, 2009
    Publication date: September 10, 2009
    Applicant: KEC CORPORATION
    Inventors: Hong Pyo Heo, Keum Hwang