Patents by Inventor Hong Q. Hou
Hong Q. Hou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8957306Abstract: A solar cell having a first subcell including a germanium (Ge) substrate having a diffusion region doped with n-type dopants including phosphorus and arsenic, wherein the upper portion of such diffusion region has a higher concentration of phosphorus (P) atoms than arsenic (As) atoms, and a second subcell including a layer of either gallium arsenide (GaAs) or indium gallium arsenide (InGaAs) disposed over the substrate.Type: GrantFiled: March 3, 2008Date of Patent: February 17, 2015Inventors: Mark A. Stan, Nein Y. Li, Frank A. Spadafora, Hong Q. Hou, Paul R. Sharps, Navid S. Fatemi
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Patent number: 8859886Abstract: Methods of fabricating multijunction solar cells that may include providing a substrate, and depositing a nucleation first layer over and directly in contact with the substrate. The methods may also include depositing a second layer containing an arsenic dopant over the nucleation layer. The nucleation layer may serve as a diffusion barrier to the arsenic dopant such that diffusion of the arsenic dopant into the substrate is limited in depth by the nucleation layer. The methods may also include depositing a sequence of layers over the second layer forming at least one solar subcell.Type: GrantFiled: April 8, 2010Date of Patent: October 14, 2014Assignee: Emcore Solar Power, Inc.Inventors: Mark A. Stan, Nein Y. Li, Frank A. Spadafora, Hong Q. Hou, Paul R. Sharps, Navid S. Fatemi
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Publication number: 20100240171Abstract: A multijunction solar cell is fabricated according to an embodiment by providing a substrate, depositing a nucleation first layer over and directly in contact with the substrate, depositing a second layer containing an arsenic dopant over the nucleation layer and depositing a sequence of layers over the second layer forming at least one solar subcell. The nucleation layer serves as a diffusion barrier to the arsenic dopant such that diffusion of the arsenic dopant into the substrate is limited in depth by the nucleation layer.Type: ApplicationFiled: April 8, 2010Publication date: September 23, 2010Applicant: Emcore Solar Power, Inc.Inventors: Mark A. Stan, Nein Y. Li, Frank A. Spadafora, Hong Q. Hou, Paul R. Sharps, Navid S. Fatemi
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Patent number: 7629240Abstract: Dopant diffusion into semiconductor material is controlled during fabrication of a semiconductor structure by depositing a nucleation layer over a first layer of the semiconductor structure and depositing a device layer containing the dopant over the nucleation layer. The nucleation layer serves as a diffusion barrier by limiting in depth the diffusion of the dopant into the first layer. The dopant can include arsenic (As).Type: GrantFiled: June 2, 2005Date of Patent: December 8, 2009Assignee: Emcore Solar Power, Inc.Inventors: Mark A. Stan, Nein Y. Li, Frank A. Spadafora, Hong Q. Hou, Paul R. Sharps, Navid S. Fatemi
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Publication number: 20080149177Abstract: Apparatus and Method for Optimizing the Efficiency of Germanium Junctions in Multi-Junction Solar Cells. In a preferred embodiment, an indium gallium phosphide (InGaP) nucleation layer is disposed between the germanium (Ge) substrate and the overlying dual-junction epilayers for controlling the diffusion depth of the n-doping in the germanium junction. Specifically, by acting as a diffusion barrier to arsenic (As) contained in the overlying epilayers and as a source of n-type dopant for forming the germanium junction, the nucleation layer enables the growth time and temperature in the epilayer device process to be minimized without compromising the integrity of the dual-junction epilayer structure. This in turn allows the arsenic diffusion into the germanium substrate to be optimally controlled by varying the thickness of the nucleation layer.Type: ApplicationFiled: March 3, 2008Publication date: June 26, 2008Applicant: EMCORE CORPORATIONInventors: Mark A. Stan, Nein Y. Li, Frank A. Spadafora, Hong Q. Hou, Paul R. Sharps, Navid S. Fatemi
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Patent number: 7339109Abstract: Apparatus and Method for Optimizing the Efficiency of Germanium Junctions in Multi-Junction Solar Cells. In a preferred embodiment, an indium gallium phosphide (InGaP) nucleation layer is disposed between the germanium (Ge) substrate and the overlying dual-junction epilayers for controlling the diffusion depth of the n-doping in the germanium junction. Specifically, by acting as a diffusion barrier to arsenic (As) contained in the overlying epilayers and as a source of n-type dopant for forming the germanium junction, the nucleation layer enables the growth time and temperature in the epilayer device process to be minimized without compromising the integrity of the dual-junction epilayer structure. This in turn allows the arsenic diffusion into the germanium substrate to be optimally controlled by varying the thickness of the nucleation layer.Type: GrantFiled: June 19, 2001Date of Patent: March 4, 2008Assignee: Emcore CorporationInventors: Mark A. Stan, Nein Y. Li, Frank A. Spadafora, Hong Q. Hou, Paul R. Sharps, Navid S. Fatemi
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Patent number: 6936483Abstract: Apparatus and method for on-wafer burn-in of a semiconductor device. In a preferred embodiment, the present invention is realized using an auto-prober commonly used in scan-testing of semiconductor devices. Specifically, in one embodiment, the auto-prober is programmed to sequentially apply an elevated current to each semiconductor device on a wafer. During the application of the elevated current, which substantially exceeds the normal operating current of the device, performance characteristics of the device, including its output power, is detected and registered. Preferably, each device is subjected to multiple scans by the elevated current. The device's performance characteristics is then analyzed. If a device exhibits consistent power output over different scans, it is not likely to suffer from infant mortality. If the device exhibits a shift in power output over successive scans, the device is likely to run into early failure and should be rejected.Type: GrantFiled: September 23, 2003Date of Patent: August 30, 2005Assignee: Emcore CorporationInventors: Hong Q. Hou, Charlie X. Wang, Wenlin Luo
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Patent number: 6863453Abstract: An apparatus and method of modular manufacturing process for a parallel optical transmitter, receiver and/or transceiver is disclosed. The modular process assembles an array of optoelectronic devices to an array header to form an optoelectronic array package. Once the optoelectronic array package is assembled, it is tested and verified the functionality and alignment between the optoelectronic devices and optical fibers. The optoelectronic array package is subsequently coupled to an optical lens array to form an array optical subassembly. After the array optical subassembly is tested, it is coupled to an optical fiber connector to form an optical module. The optical module is then tested to verify its functionality and alignment.Type: GrantFiled: January 28, 2003Date of Patent: March 8, 2005Assignee: Emcore CorporationInventors: Charlie X. Wang, Hong Q. Hou, Frederick B. McCormick
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Publication number: 20040146253Abstract: An apparatus and method of modular manufacturing process for a parallel optical transmitter, receiver and/or transceiver is disclosed. The modular process assembles an array of optoelectronic devices to an array header to form an optoelectronic array package. Once the optoelectronic array package is assembled, it is tested and verified the functionality and alignment between the optoelectronic devices and optical fibers. The optoelectronic array package is subsequently coupled to an optical lens array to form an array optical subassembly. After the array optical subassembly is tested, it is coupled to an optical fiber connector to form an optical module. The optical module is then tested to verify its functionality and alignment.Type: ApplicationFiled: January 28, 2003Publication date: July 29, 2004Inventors: Charlie X. Wang, Hong Q. Hou, Frederick B. McCormick
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Patent number: 6765242Abstract: An NPN double heterostructure bipolar transistor (DHBT) is disclosed with a base region comprising a layer of p-type-doped indium gallium arsenide nitride (InGaAsN) sandwiched between n-type-doped collector and emitter regions. The use of InGaAsN for the base region lowers the transistor turn-on voltage, Von, thereby reducing power dissipation within the device. The NPN transistor, which has applications for forming low-power electronic circuitry, is formed on a gallium arsenide (GaAs) substrate and can be fabricated at commercial GaAs foundries. Methods for fabricating the NPN transistor are also disclosed.Type: GrantFiled: April 11, 2000Date of Patent: July 20, 2004Assignees: Sandia Corporation, Emcore CorporationInventors: Ping-Chih Chang, Albert G. Baca, Nein-Yi Li, Hong Q. Hou, Carol I. H. Ashby
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Publication number: 20040119486Abstract: Apparatus and method for on-wafer burn-in of a semiconductor device. In a preferred embodiment, the present invention is realized using an auto-prober commonly used in scan-testing of semiconductor devices. Specifically, in one embodiment, the auto-prober is programmed to sequentially apply an elevated current to each semiconductor device on a wafer. During the application of the elevated current, which substantially exceeds the normal operating current of the device, performance characteristics of the device, including its output power, is detected and registered. Preferably, each device is subjected to multiple scans by the elevated current. The device's performance characteristics is then analyzed. If a device exhibits consistent power output over different scans, it is not likely to suffer from infant mortality. If the device exhibits a shift in power output over successive scans, the device is likely to run into early failure and should be rejected.Type: ApplicationFiled: September 23, 2003Publication date: June 24, 2004Inventors: Hong Q. Hou, Charlie X. Wang, Wenlin Luo
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Patent number: 6677172Abstract: Apparatus and method for on-wafer burn-in of a semiconductor device. In a preferred embodiment, the present invention is realized using an auto-prober commonly used in scan-testing of semiconductor devices. Specifically, in one embodiment, the auto-prober is programmed to sequentially apply an elevated current to each semiconductor device on a wafer. During the application of the elevated current, which substantially exceeds the normal operating current of the device, performance characteristics of the device, including its output power, is detected and registered. Preferably, each device is subjected to multiple scans by the elevated current. The device's performance characteristics is then analyzed. If a device exhibits consistent power output over different scans, it is not likely to suffer from infant mortality. If the device exhibits a shift in power output over successive scans, the device is likely to run into early failure and should be rejected.Type: GrantFiled: June 27, 2002Date of Patent: January 13, 2004Assignee: Emcore CorporationInventors: Hong Q. Hou, Charlie X. Wang, Wenlin Luo
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Publication number: 20040002175Abstract: Apparatus and method for on-wafer burn-in of a semiconductor device. In a preferred embodiment, the present invention is realized using an auto-prober commonly used in scan-testing of semiconductor devices. Specifically, in one embodiment, the auto-prober is programmed to sequentially apply an elevated current to each semiconductor device on a wafer. During the application of the elevated current, which substantially exceeds the normal operating current of the device, performance characteristics of the device, including its output power, is detected and registered. Preferably, each device is subjected to multiple scans by the elevated current. The device's performance characteristics is then analyzed. If a device exhibits consistent power output over different scans, it is not likely to suffer from infant mortality. If the device exhibits a shift in power output over successive scans, the device is likely to run into early failure and should be rejected.Type: ApplicationFiled: June 27, 2002Publication date: January 1, 2004Inventors: Hong Q. Hou, Charlie X. Wang, Wenlin Luo
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Publication number: 20020040727Abstract: Apparatus and Method for Optimizing the Efficiency of Germanium Junctions in Multi-Junction Solar Cells. In a preferred embodiment, an indium gallium phosphide (InGaP) nucleation layer is disposed between the germanium (Ge) substrate and the overlying dual-junction epilayers for controlling the diffusion depth of the n-doping in the germanium junction. Specifically, by acting as a diffusion barrier to arsenic (As) contained in the overlying epilayers and as a source of n-type dopant for forming the germanium junction, the nucleation layer enables the growth time and temperature in the epilayer device process to be minimized without compromising the integrity of the dual-junction epilayer structure. This in turn allows the arsenic diffusion into the germanium substrate to be optimally controlled by varying the thickness of the nucleation layer.Type: ApplicationFiled: June 19, 2001Publication date: April 11, 2002Inventors: Mark A. Stan, Nein Y. Li, Frank A. Spadafora, Hong Q. Hou, Paul R. Sharps, Navid S. Fatemi
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Patent number: 6258615Abstract: A process for forming an array of vertical cavity optical resonant structures wherein the structures in the array have different detection or emission wavelengths. The process uses selective area growth (SAG) in conjunction with annular masks of differing dimensions to control the thickness and chemical composition of the materials in the optical cavities in conjunction with a metalorganic vapor phase epitaxy (MOVPE) process to build these arrays.Type: GrantFiled: November 12, 1998Date of Patent: July 10, 2001Assignee: Sandia CorporationInventors: Hong Q. Hou, Michael E. Coltrin, Kent D. Choquette
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Patent number: 6248992Abstract: A photoconductive semiconductor switch with tailored doping profile zones beneath and extending laterally from the electrical contacts to the device. The zones are of sufficient depth and lateral extent to isolate the contacts from damage caused by the high current filaments that are created in the device when it is turned on. The zones may be formed by etching depressions into the substrate, then conducting epitaxial regrowth in the depressions with material of the desired doping profile. They may be formed by surface epitaxy. They may also be formed by deep diffusion processes. The zones act to reduce the energy density at the contacts by suppressing collective impact ionization and formation of filaments near the contact and by reducing current intensity at the contact through enhanced current spreading within the zones.Type: GrantFiled: June 18, 1999Date of Patent: June 19, 2001Assignee: Sandia CorporationInventors: Albert G. Baca, Guillermo M. Loubriel, Alan Mar, Fred J Zutavern, Harold P. Hjalmarson, Andrew A. Allerman, Thomas E. Zipperian, Martin W. O'Malley, Wesley D. Helgeson, Gary J. Denison, Darwin J. Brown, Charles T. Sullivan, Hong Q. Hou
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Patent number: 5944913Abstract: A high-efficiency 3- or 4-junction solar cell is disclosed with a theoretical AM0 energy conversion efficiency of about 40%. The solar cell includes p-n junctions formed from indium gallium arsenide nitride (InGaAsN), gallium arsenide (GaAs) and indium gallium aluminum phosphide (InGaAlP) separated by n-p tunnel junctions. An optional germanium (Ge) p-n junction can be formed in the substrate upon which the other p-n junctions are grown. The bandgap energies for each p-n junction are tailored to provide substantially equal short-circuit currents for each p-n junction, thereby eliminating current bottlenecks and improving the overall energy conversion efficiency of the solar cell. Additionally, the use of an InGaAsN p-n junction overcomes super-bandgap energy losses that are present in conventional multi-junction solar cells. A method is also disclosed for fabricating the high-efficiency 3- or 4-junction solar cell by metal-organic chemical vapor deposition (MOCVD).Type: GrantFiled: November 26, 1997Date of Patent: August 31, 1999Assignee: Sandia CorporationInventors: Hong Q. Hou, Kitt C. Reinhardt