Abstract: Providing recommendations for first responders can include receiving, using a processor, real time sensor data from a plurality of sensors, correlating, using the processor, the real time sensor data with historical data for a plurality of prior incidents to determine a selected prior incident matching the real time sensor data, and determining a recommended next action from an operating procedure based upon a next action taken for the selected prior incident.

Abstract: Providing recommendations for first responders can include receiving, using a processor, real time sensor data from a plurality of sensors, correlating, using the processor, the real time sensor data with historical data for a plurality of prior incidents to determine a selected prior incident matching the real time sensor data, and determining a recommended next action from an operating procedure based upon a next action taken for the selected prior incident.

Abstract: In a particular embodiment, a method includes receiving a testing activation signal at a controller coupled to a semiconductor device. The method further includes biasing a well of at least one transistor of the semiconductor device in response to the received testing activation signal. The bias is provided by a biasing circuit that is responsive to the controller. While the well is biased, a test of the semiconductor device is performed to generate testing data.

Abstract: In a particular embodiment, a method includes receiving a testing activation signal at a controller coupled to a semiconductor device. The method further includes biasing a well of at least one transistor of the semiconductor device in response to the received testing activation signal. The bias is provided by a biasing circuit that is responsive to the controller. While the well is biased, a test of the semiconductor device is performed to generate testing data.

Abstract: A method and apparatus for performing a memory dump. The method includes providing a memory location from a debugger to a memory array through a BIST wrapper, and receiving data by the debugger read from the memory location in the memory array. The method can include sending a dump enable signal from the debugger, and the BIST wrapper selectively providing the memory location to the memory array in response to the dump enable signal. The method can include sending the dump enable signal to a multiplexer coupled to a register in the BIST wrapper, the dump enable signal causing the multiplexer to load the register with the memory location. The method can include asynchronously sending a write disable signal to the memory array before reading the data from the memory location. The received data can be selected from a larger set of data read from the memory location.

Abstract: In a particular embodiment, a method is disclosed that includes mapping failing bit positions within multiple scan chains to memory locations of a memory mask. The method also includes executing logic built-in self-test (LBIST) testing on a semiconductor device using the memory mask to selectively mask certain results within the multiple scan chains. The results are associated with performance of LBIST testing on the semiconductor device.

Abstract: In a particular embodiment, a method includes receiving a testing activation signal at a controller coupled to a semiconductor device. The method further includes biasing a well of at least one transistor of the semiconductor device in response to the received testing activation signal. The bias is provided by a biasing circuit that is responsive to the controller. While the well is biased, a test of the semiconductor device is performed to generate testing data.

Abstract: A feedback scan isolation and bypass architecture apparatus and method. The apparatus includes core logic, and input and output multiplexers. The input multiplexer selectively provides a functional input or the core output to the core input based on a test signal. The output multiplexer selectively provides the core output or the input multiplexer output to a functional output based on the test signal. When the test signal indicates core feedback testing, the output multiplexer outputs the core output and the input multiplexer feeds back the core output to the core input. When the test signal indicates bypass testing, the input multiplexer outputs the functional input and the output multiplexer outputs the functional input bypassing the core logic. Logic can block the feedback or bypass signals when there are timing issues. Logic can modify the number of feedback or bypass signals when the number of functional inputs and outputs are different.

Abstract: A method and apparatus for performing a memory dump. The method includes providing a memory location from a debugger to a memory array through a BIST wrapper, and receiving data by the debugger read from the memory location in the memory array. The method can include sending a dump enable signal from the debugger, and the BIST wrapper selectively providing the memory location to the memory array in response to the dump enable signal. The method can include sending the dump enable signal to a multiplexer coupled to a register in the BIST wrapper, the dump enable signal causing the multiplexer to load the register with the memory location. The method can include asynchronously sending a write disable signal to the memory array before reading the data from the memory location. The received data can be selected from a larger set of data read from the memory location.

Abstract: In a particular embodiment, a method is disclosed that includes mapping failing bit positions within multiple scan chains to memory locations of a memory mask. The method also includes executing logic built-in self-test (LBIST) testing on a semiconductor device using the memory mask to selectively mask certain results within the multiple scan chains. The results are associated with performance of LBIST testing on the semiconductor device.

Abstract: In a particular embodiment, a method includes receiving a testing activation signal at a controller coupled to a semiconductor device. The method further includes biasing a well of at least one transistor of the semiconductor device in response to the received testing activation signal. The bias is provided by a biasing circuit that is responsive to the controller. While the well is biased, a test of the semiconductor device is performed to generate testing data.

Abstract: A signal duration measurement system compares a known duration, T1, of a test data signal with the duration, T2, of a state of a signal under test. In one embodiment, if T2 compares favorably with T1, then the circuit generating the signal under test ‘passes.’ Otherwise the signal under test ‘fails,’ and a problem has been identified. Furthermore, in one embodiment, T1 can be selectively adjusted to more accurately measure T2. In one embodiment, the test data signal is allowed to travel a signal path, having a known signal propagation delay time, during a single state of the signal under test. The data signal at the beginning of the state, e.g. during the rise of the signal under test, is compared to the data signal captured at the end of the state, e.g. during the fall of the signal under test. If the initial and captured data signals are the same, then the duration of the state of the signal under test is greater than or equal to the signal propagation delay time.

Abstract: It has been discovered that initialization of a memory array can be improved by setting the nodes of the memory array to a predetermined value automatically upon applying power to the integrated circuit. Data input nodes and a memory write enable node are configured to store the predetermined values on the nodes of the memory array in response to successive enablement of word lines corresponding to the nodes of the memory array and automatic reset of the word lines. Circuitry included for initializing control and data signals of the memory array are effectively disabled upon termination of the initialization. Inclusion of circuitry that initiates and terminates the initialization obviates an additional input/output pin for this purpose.

Abstract: Embodiments of the present invention provide a method and apparatus for debugging an integrated circuit. In particular, one embodiment of the present invention includes steps of: (a) retrieving data from a design data base, and creating a design pattern in a pattern format, which design pattern includes stimulus data for stimuli to be applied to the integrated circuit and design response data for expected responses to the stimuli; (b) generating, responsive to the design pattern, a tester pattern and a test program for input to a tester; (c) testing the integrated circuit in the tester, responsive to the tester pattern and the test program, and generating a datalog that comprises test response data; and (d) generating a file, responsive to the datalog, wherein the test response data are reformatted into the pattern format.

Abstract: Signal state durations, such as the pulse-width, of on-chip signals are often critical to the successful operation of an integrated circuit. The signal state durations measured by on-chip technology provide signal state duration information to an on-chip signal state duration control system. The signal state duration control system uses the information to adjust the signal state duration of an on-chip signal. In one embodiment, the signal state duration of the on-chip signal is the pulse width of the on-chip signal. The signal duration measurement and adjustment system is, for example, useful for measuring the state duration of signals such as self-resetting signals, which are difficult to externally measure and adjust signal state durations using on-chip technology.

Abstract: A method of generating a test vector pattern for an array, including determining a failure of a test of the array, defining a type of test vector pattern to generate using a graphical user interface, generating the test vector pattern, and testing the array using the test vector pattern. A test vector pattern generation tool, including an array, a test vector pattern, and a graphical user interface generating the test vector pattern. The array is tested using the custom test vector pattern.

Abstract: Signal state durations, such as the pulse-width, of on-chip signals are often critical to the successful operation of an integrated circuit. Commonly assigned patent application Ser. No. 10/292329 entitled “On-Chip Measurement of Signal State Duration”, describes examples of a signal state duration measurement system technology that measures signal state durations using on-chip technology. The signal state durations measured by on-chip technology provide signal state duration information to an on-chip signal state duration control system. The signal state duration control system uses the information to adjust the signal state duration of an on-chip signal. In one embodiment, the signal state duration of the on-chip signal is the pulse width of the on-chip signal.

Abstract: A signal duration measurement system compares a known duration, T1, of a test data signal with the duration, T2, of a state of a signal under test. In one embodiment, if T2 compares favorably with T1, then the circuit generating the signal under test ‘passes.’ Otherwise the signal under test ‘fails,’ and a problem has been identified. Furthermore, in one embodiment, T1 can be selectively adjusted to more accurately measure T2. In one embodiment, the test data signal is allowed to travel a signal path, having a known signal propagation delay time, during a single state of the signal under test. The data signal at the beginning of the state, e.g. during the rise of the signal under test, is compared to the data signal captured at the end of the state, e.g. during the fall of the signal under test. If the initial and captured data signals are the same, then the duration of the state of the signal under test is greater than or equal to the signal propagation delay time.

Abstract: Embodiments of the present invention provide a method and apparatus for debugging an integrated circuit. In particular, one embodiment of the present invention includes steps of: (a) retrieving data from a design data base, and creating a design pattern in a pattern format, which design pattern includes stimulus data for stimuli to be applied to the integrated circuit and design response data for expected responses to the stimuli; (b) generating, responsive to the design pattern, a tester pattern and a test program for input to a tester; (c) testing the integrated circuit in the tester, responsive to the tester pattern and the test program, and generating a datalog that comprises test response data; and (d) generating a file, responsive to the datalog, wherein the test response data are reformatted into the pattern format.

Abstract: A method of generating a test vector pattern for an array, including determining a failure of a test of the array, defining a type of test vector pattern to generate using a graphical user interface, generating the test vector pattern, and testing the array using the test vector pattern. A test vector pattern generation tool, including an array, a test vector pattern, and a graphical user interface generating the test vector pattern. The array is tested using the custom test vector pattern.