Abstract: Polishing pads are provided that include a substrate for a polishing pad and a plurality of spaced apart members on the substrate and protruding from the substrate. The plurality of members include at least one abrasive layer and at least one chemical additive layer. Related methods of fabricating polishing pads are also provided herein.

Abstract: A contact structure includes a lower conductive pattern disposed on a predetermined region of a semiconductor substrate. The lower conductive layer has a concave region at a predetermined region of a top surface thereof. An embedding conductive layer fills the concave region. The top surface of the embedding conductive layer is placed at least as high as the height of the flat top surface of the lower conductive pattern. A mold layer is disposed to cover the semiconductor substrate, the lower conductive pattern and the embedding conductive layer. An upper conductive pattern is arranged in an intaglio pattern. The intaglio pattern is disposed in the mold layer to expose a predetermined region of the embedding conductive layer.

Abstract: An inductor for a system-on-a-chip and a method for manufacturing the inductor are disclosed. The inductor comprises a conductive line formed by connecting a plurality of conductive patterns grown from a seed layer formed on a lower wiring. The method comprises using an electrolytic plating process or an electroless plating process to grow the plurality of adjacent conductive patterns from the seed layer until they become connected. The method also enables adjusting the height and width of the conductive line to desired levels.

Abstract: A method of manufacturing a semiconductor element, includes forming a lower metal wiring layer and an interlayer insulating film on a substrate, forming an opening through the interlayer insulating film, such that the opening is in communication with an upper surface of the lower metal wiring layer, cleaning the opening, forming a metal wiring line protecting film in the opening, such that the metal wiring line protecting film covers the lower metal wiring layer, washing the opening to remove the metal wiring line protecting film, such that a top surface of the lower metal wiring layer is exposed, and drying the substrate.

Abstract: Polishing apparatus and related methods employ aligned first and second magnetic field sources to adjust the compressive force and/or pressure applied by a carrier head against a target workpiece (such as a wafer) by selectively and controllably generating a repellant or attractive force between the two magnetic field sources.

Abstract: The present invention discloses a metal-insulator-metal (MIM) capacitor and a method for fabricating the MIM capacitor, comprising forming a bottom insulation layer, a capacitor electrode material layer, and a hard mask material layer on a semiconductor substrate having a metal wire thereon; forming a hard mask by etching the hard mask material layer using a photosensitive mask; forming a capacitor electrode by etching the capacitor electrode material layer using the hard mask as an etching mask; and forming a top insulation layer on an entire surface of the semiconductor.

Abstract: An inductor for a system-on-a-chip and a method for manufacturing the inductor are disclosed. The inductor comprises a conductive line formed by connecting a plurality of conductive patterns grown from a seed layer formed on a lower wiring. The method comprises using an electrolytic plating process or an electroless plating process to grow the plurality of adjacent conductive patterns from the seed layer until they become connected. The method also enables adjusting the height and width of the conductive line to desired levels.

Abstract: Methods are provided for fabricating a semiconductor device that include the steps of: sequentially forming a metal interconnection and a protecting layer on a semiconductor substrate; forming a contact hole on the protecting layer; isolating the contact hole by forming a molding layer and an etching stop layer stacked thereon; forming a sacrificial layer on the etching stop layer so as to fill the contact hole; forming a photoresist layer with an opening so as to expose the sacrificial layer and such that the opening of the photoresist layer aligns with the contact hole; forming a trench in the molding layer to penetrate the sacrificial layer and the etching stop layer; and performing a wet etching on the semiconductor substrate having the trench to remove the photoresist layer and the sacrificial layer, wherein the wet etching step is performed using an organic compound and fluoride ion-based buffered solution.

Abstract: A method of manufacturing a semiconductor element, includes forming a lower metal wiring layer and an interlayer insulating film on a substrate, forming an opening through the interlayer insulating film, such that the opening is in communication with an upper surface of the lower metal wiring layer, cleaning the opening, forming a metal wiring line protecting film in the opening, such that the metal wiring line protecting film covers the lower metal wiring layer, washing the opening to remove the metal wiring line protecting film, such that a top surface of the lower metal wiring layer is exposed, and drying the substrate.

Abstract: A contact structure includes a lower conductive pattern disposed on a predetermined region of a semiconductor substrate. The lower conductive layer has a concave region at a predetermined region of a top surface thereof. An embedding conductive layer fills the concave region. The top surface of the embedding conductive layer is placed at least as high as the height of the flat top surface of the lower conductive pattern. A mold layer is disposed to cover the semiconductor substrate, the lower conductive pattern and the embedding conductive layer. An upper conductive pattern is arranged in an intaglio pattern. The intaglio pattern is disposed in the mold layer to expose a predetermined region of the embedding conductive layer.

Abstract: A method for use in manufacturing a semiconductor device includes forming a photoresist pattern on a substrate, performing first etching process in which an initial trench is formed using the photoresist pattern as a mask, and performing second distinct etching process to enlarge the initial trench. Thus, the initial trench can be formed using the photoresist pattern having a stable structure. Thereafter, the trench is enlarged using an etching solution having a composition based on the material in which the initial trench is formed, e.g., silicon substrate or an insulation film. Therefore, a metal wiring, an isolation film or a contact can be formed in the enlarged trench to desired dimensions.

Abstract: A method for use in manufacturing a semiconductor device includes forming a photoresist pattern on a substrate, performing first etching process in which an initial trench is formed using the photoresist pattern as a mask, and performing second distinct etching process to enlarge the initial trench. Thus, the initial trench can be formed using the photoresist pattern having a stable structure. Thereafter, the trench is enlarged using an etching solution having a composition based on the material in which the initial trench is formed, e.g., a silicon substrate or an insulation film. Therefore, a metal wiring, an isolation film or a contact can be formed in the enlarged trench to desired dimensions.

Abstract: A contact structure includes a lower conductive pattern disposed on a predetermined region of a semiconductor substrate. The lower conductive layer has a concave region at a predetermined region of a top surface thereof. An embedding conductive layer fills the concave region. The top surface of the embedding conductive layer is placed at least as high as the height of the flat top surface of the lower conductive pattern. A mold layer is disposed to cover the semiconductor substrate, the lower conductive pattern and the embedding conductive layer. An upper conductive pattern is arranged in an intaglio pattern. The intaglio pattern is disposed in the mold layer to expose a predetermined region of the embedding conductive layer.

Abstract: A method of forming a metal pattern using a selective electroplating process is provided. First, a dielectric layer is formed on an underlying layer. Then, a trench defining blanket region is formed by patterning the dielectric layer. A diffusion barrier layer is conformally formed in the trench and on the blanket region. A polishing/plating stop layer and an upper seed layer are conformally formed on the diffusion barrier layer in a successive manner. The polishing/plating layer in the blanket region is exposed by selectively removing the upper seed layer in the blanket region, and, at the same time, a seed layer pattern remaining in the trenches is formed. An upper conductive layer is formed to fill the trench surrounded by the seed layer pattern using an electroplating process. Then, the dielectric layer in the blanket region is exposed by planarizing the upper conductive layer, the polishing/plating stop layer, the seed layer pattern, and the diffusion barrier layer.

Abstract: Polishing apparatus and related methods employ aligned first and second magnetic field sources to adjust the compressive force and/or pressure applied by a carrier head against a target workpiece (such as a wafer) by selectively and controllably generating a repellant or attractive force between the two magnetic field sources.

Abstract: Polishing apparatus and related methods employ aligned first and second magnetic field sources to adjust the compressive force and/or pressure applied by a carrier head against a target workpiece (such as a wafer) by selectively and controllably generating a repellant or attractive force between the two magnetic field sources.

Abstract: A cleaning apparatus includes upper and lower nozzle assemblies supplying a cleaning liquid to edge and bottom sections of a semiconductor substrate. The upper nozzle assembly has a first nozzle supplying the cleaning liquid onto the edge section, and second and third nozzles supplying a nitrogen gas for preventing the cleaning liquid from moving into a center portion of the semiconductor substrate. The cleaning liquid supplied to the edge section flows from the edge section towards a side section of the semiconductor substrate due to the rotation of the semiconductor substrate. An ultrasonic wave generator is provided above the edge section for generating ultrasonic waves. The ultrasonic waves are applied to the cleaning liquid supplied onto the edge and bottom sections, thereby improving the cleaning efficiency. The cleaning apparatus has a guide to guide the cleaning liquid supplied to the edge section toward the side section.

Abstract: In a method for filling a hole with a metal, an insulating layer, a first mask layer and a second mask layer are successively formed on a semiconductor substrate. The first and second mask layers are etched using a photoresist pattern to form first and second masks. The first mask layer pattern is selectively etched using an etchant, the first mask layer pattern having a higher etching selectivity than the second layer pattern with respect to the etchant, to form a third mask layer pattern having a broadened opening. The insulating layer is etched using the second mask to form a hole in the insulating layer. A metal layer is formed in the hole and the third opening. The metal layer is planarized to form a metal plug buried in the hole without recesses or voids.

Abstract: A cleaning apparatus includes upper and lower nozzle assemblies supplying a cleaning liquid to edge and bottom sections of a semiconductor substrate. The upper nozzle assembly has a first nozzle supplying the cleaning liquid onto the edge section, and second and third nozzles supplying a nitrogen gas for preventing the cleaning liquid from moving into a center portion of the semiconductor substrate. The cleaning liquid supplied to the edge section flows from the edge section towards a side section of the semiconductor substrate due to the rotation of the semiconductor substrate. An ultrasonic wave generator is provided above the edge section for generating ultrasonic waves. The ultrasonic waves are applied to the cleaning liquid supplied onto the edge and bottom sections, thereby improving the cleaning efficiency. The cleaning apparatus has a guide to guide the cleaning liquid supplied to the edge section toward the side section.

Abstract: There is provided a chemical mechanical polishing apparatus, which may include a polishing table rotated by a polishing table motor and having a pad thereon, a carrier head located above the polishing table to be rotatable by the driving of a carrier head motor and having a wafer located under the bottom thereof, a slurry supplier for supplying a slurry to the upper portion of the polishing table, a first polishing end point detector for detecting a polishing end point through the temperature change of the temperature sensor, at least one temperature sensor for detecting the temperature of a polishing region (the wafer, the pad, and the slurry), and a second polishing end point detector for detecting a polishing end point from the changes of load current, voltage, and resistance of the carrier head motor.