Patents by Inventor Hong Shen

Hong Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180248044
    Abstract: A flexible substrate structure including a flexible substrate, a first dielectric layer, a metal-containing layer and a second dielectric layer is provided. The first dielectric layer is located on the flexible substrate. The metal-containing layer has a reflectivity greater than 15% and a heat transfer coefficient greater than 2 W/m-K. The metal-containing layer is disposed between the first dielectric layer and the second dielectric layer, and the second dielectric layer is an inorganic material layer. A flexible transistor including the above-mentioned flexible substrate structure and a method for fabricating the same are also provided.
    Type: Application
    Filed: February 26, 2018
    Publication date: August 30, 2018
    Inventors: WEN-HSIEN HUANG, JIA-MIN SHIEH, CHANG-HONG SHEN
  • Publication number: 20180233447
    Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A, 120E.B) are provided above the substrate that wrap around the conductive vias' protrusions (114?) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.
    Type: Application
    Filed: April 13, 2018
    Publication date: August 16, 2018
    Applicant: Invensas Corporation
    Inventors: Cyprian Emeka UZOH, Charles G. WOYCHIK, Arkalgud R. SITARAM, Hong SHEN, Zhuowen SUN, Liang WANG, Guilian GAO
  • Publication number: 20180221792
    Abstract: Disclosed are capsule/tube connector/tube assemblies that eliminate a connection point in a filter capsule apparatus. A relatively soft tube is thermally or sonically bonded to a relatively hard tube connector that may have a tube receiving bore, a frustoconical tube receiving channel or a straight tube receiving channel. The tube connector is bonded to a filter capsule port. The manufacturing process can be either a one-step process bonding the tube and capsule during formation of the tube connector in one step, or a two-step process that binds the tube to the tube connector in one step and binds the tube connector to a filter capsule port in a second step. Single and dual-walled tubes may be used as well as single and dual-walled tubes having reinforcing material superposed about or embedded in the tube wall(s). A tube support collar is also disclosed.
    Type: Application
    Filed: April 3, 2018
    Publication date: August 9, 2018
    Applicant: Saint-Gobain Performance Plastics Corporation
    Inventors: ZhenWu LIN, Hong Shen
  • Patent number: 10030047
    Abstract: The present invention provides compounds of formula (I) wherein X1 to X8 and R1 to R8 are as described herein, as well as pharmaceutically acceptable salts thereof. Further the present invention is concerned with the manufacture of the compounds of formula (I), pharmaceutical compositions comprising them and their use as medicaments for the treatment of diseases and infections caused by Acinetobacter baumannii.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: July 24, 2018
    Assignee: HOFFMANN-LA ROCHE INC.
    Inventors: Alexander Alanine, Julien Beignet, Konrad Bleicher, Bernhard Fasching, Hans Hilpert, Taishan Hu, Dwight MacDonald, Stephen Jackson, Sabine Kolczewski, Carsten Kroll, Adrian Schaeublin, Hong Shen, Theodor Stoll, Helmut Thomas, Amal Wahhab, Claudia Zampaloni
  • Patent number: 10014243
    Abstract: An interposer (110) has contact pads at the top and/or bottom surfaces for connection to circuit modules (e.g. ICs 112). The interposer includes a substrate made of multiple layers (110.i). Each layer can be a substrate (110S), possibly a ceramic substrate, with circuitry. The substrates extend vertically. Multiple interposers are fabricated in a single structure (310) made of vertical layers (310.i) corresponding to the interposers' layers. The structure is diced along horizontal planes (314) to provide the interposers. An interposer's vertical conductive lines (similar to through-substrate vias) can be formed on the substrates' surfaces before dicing and before all the substrates are attached to each other. Thus, there is no need to make through-substrate holes for the vertical conductive lines. Non-vertical features can also be formed on the substrates' surfaces before the substrates are attached to each other. Other embodiments are also provided.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: July 3, 2018
    Assignee: INVENSAS CORPORATION
    Inventors: Hong Shen, Liang Wang, Gabriel Z. Guevara, Rajesh Katkar, Cyprian Emeka Uzoh, Laura Wills Mirkarimi
  • Publication number: 20180130717
    Abstract: Dies (110) with integrated circuits are attached to a wiring substrate (120), possibly an interposer, and are protected by a protective substrate (410) attached to a wiring substrate. The dies are located in cavities in the protective substrate (the dies may protrude out of the cavities). In some embodiments, each cavity surface puts pressure on the die to strengthen the mechanical attachment of the die the wiring substrate, to provide good thermal conductivity between the dies and the ambient (or a heat sink), to counteract the die warpage, and possibly reduce the vertical size. The protective substrate may or may not have its own circuitry connected to the dies or to the wiring substrate. Other features are also provided.
    Type: Application
    Filed: January 9, 2018
    Publication date: May 10, 2018
    Applicant: INVENSAS CORPORATION
    Inventors: Hong SHEN, Charles G. WOYCHIK, Arkalgud R. SITARAM
  • Publication number: 20180124927
    Abstract: A contact pad includes a solder-wettable porous network (310) which wicks the molten solder (130) and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads.
    Type: Application
    Filed: December 29, 2017
    Publication date: May 3, 2018
    Applicant: INVENSAS CORPORATION
    Inventors: Liang WANG, Rajesh KATKAR, Hong SHEN, Cyprian Emeka UZOH
  • Patent number: 9947618
    Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A, 120E.B) are provided above the substrate that wrap around the conductive vias' protrusions (114?) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: April 17, 2018
    Inventors: Cyprian Emeka Uzoh, Charles G. Woychik, Arkalgud R. Sitaram, Hong Shen, Zhuowen Sun, Liang Wang, Guilian Gao
  • Patent number: 9946712
    Abstract: A computer-implemented technique includes receiving, at a computing device including one or more processors, a user input (i) identifying a portion of a media stream being output from the computing device and (ii) indicating a request to translate the portion of the media stream from a source language to a target language. The technique includes transmitting, from the computing device, the portion of the media stream to a translation server via a network in response to receiving the user input. The technique includes receiving, at the computing device, a translated portion of the media stream from the translation server via the network, the translated portion of the media stream having been translated from the source language to the target language by the translation server. The technique also includes outputting, at the computing device, the translated portion of the media stream.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: April 17, 2018
    Assignee: GOOGLE LLC
    Inventor: Hong Shen
  • Publication number: 20180096973
    Abstract: Systems and methods for providing 3D wafer assembly with known-good-dies are provided. An example method compiles an index of dies on a semiconductor wafer and removes the defective dies to provide a wafer with dies that are all operational. Defective dies on multiple wafers may be removed in parallel, and resulting wafers with all good dies stacked in 3D wafer assembly. In an implementation, the spaces left by removed defective dies may be filled at least in part with operational dies or with a fill material. Defective dies may be replaced either before or after wafer-to-wafer assembly to eliminate production of defective stacked devices, or the spaces may be left empty. A bottom device wafer may also have its defective dies removed or replaced, resulting in wafer-to-wafer assembly that provides 3D stacks with no defective dies.
    Type: Application
    Filed: December 7, 2017
    Publication date: April 5, 2018
    Applicant: Invensas Corporation
    Inventors: Hong Shen, Liang Wang, Guilian Gao
  • Publication number: 20180078465
    Abstract: A dental self-adhesive resin cement is provided comprising a two-component system. A first catalyst component includes one or more acidic monomers. A second base component includes one or more basic fillers. The mixture of the first and second components is polymerizable and has an initial pH that is acidic immediately after mixing and a pH of at least about pH 8 after polymerization.
    Type: Application
    Filed: September 12, 2017
    Publication date: March 22, 2018
    Inventors: Liang Chen, Byoung In Suh, Hong Shen, Christine Gleave
  • Publication number: 20180076278
    Abstract: A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first region. The capacitor has a pair of electrodes, each coupled to one of a pair of conductive pads, at least one of which is disposed on a lower surface of the handle wafer. An interposer having an upper surface with a conductive pad and at least one semiconductor die disposed thereon is also provided. The die has an integrated circuit that is electroconductively coupled to a redistribution layer (RDL) of the interposer. The lower surface of the handle wafer is bonded to the upper surface of the interposer such that the die is disposed below or within the cavity and the electroconductive pad of the handle wafer is bonded to the electroconductive pad of the interposer in a metal-to-metal bond.
    Type: Application
    Filed: November 6, 2017
    Publication date: March 15, 2018
    Applicant: INVENSAS CORPORATION
    Inventors: Liang WANG, Hong SHEN, Rajesh KATKAR
  • Patent number: 9905523
    Abstract: Two microelectronic components (110, 120), e.g. a die and an interposer, are bonded to each other. One of the components' contact pads (110C) include metal, and the other component has silicon (410) which reacts with the metal to form metal silicide (504). Then a hole (510) is made through one of the components to reach the metal silicide and possibly even the unreacted metal (110C) of the other component. The hole is filled with a conductor (130), possibly metal, to provide a conductive via that can be electrically coupled to contact pads (120C.B) attachable to other circuit elements or microelectronic components, e.g. to a printed circuit board.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: February 27, 2018
    Assignee: INVENSAS CORPORATION
    Inventors: Hong Shen, Liang Wang, Arkalgud R. Sitaram
  • Patent number: 9905507
    Abstract: A combined interposer (120) includes multiple constituent interposers (120.i), each with its own substrate (120.iS) and with a circuit layer (e.g. redistribution layer) on top and/or bottom of the substrate. The top circuit layers can be part of a common circuit layer (120R.T) which can interconnect different interposers. Likewise, the bottom circuit layers can be part of a common circuit layer (120R.B). The constituent interposer substrates (120.iS) are initially part of a common wafer, and the common top circuit layer is fabricated before separation of the constituent interposer substrates from the wafer. Use of separated substrates reduces stress compared to use of a single large substrate. Other features are also provided.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: February 27, 2018
    Assignee: INVENSAS CORPORATION
    Inventors: Hong Shen, Zhuowen Sun, Charles G. Woychik, Arkalgud Sitaram
  • Patent number: 9905547
    Abstract: A chipset with light energy harvester, includes a substrate, a functional element layer, and a light energy harvesting layer, both are stacked vertically on the substrate, and an interconnects connected between the functional element layer and the light energy harvesting layer.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: February 27, 2018
    Assignee: NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Chang-Hong Shen, Jia-Min Shieh, Wen-Hsien Huang, Tsung-Ta Wu, Chih-Chao Yang, Tung-Ying Hsieh
  • Patent number: 9899281
    Abstract: Dies (110) with integrated circuits are attached to a wiring substrate (120), possibly an interposer, and are protected by a protective substrate (410) attached to a wiring substrate. The dies are located in cavities in the protective substrate (the dies may protrude out of the cavities). In some embodiments, each cavity surface puts pressure on the die to strengthen the mechanical attachment of the die the wiring substrate, to provide good thermal conductivity between the dies and the ambient (or a heat sink), to counteract the die warpage, and possibly reduce the vertical size. The protective substrate may or may not have its own circuitry connected to the dies or to the wiring substrate. Other features are also provided.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: February 20, 2018
    Assignee: INVENSAS CORPORATION
    Inventors: Hong Shen, Charles G. Woychik, Arkalgud R. Sitaram
  • Patent number: 9890167
    Abstract: The present invention relates to compounds of the formula (I), or pharmaceutically acceptable salts, enantiomer or diastereomer thereof, wherein R1 to R4 are as described above. The compounds may be useful for the treatment or prophylaxis of hepatitis B virus infection.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: February 13, 2018
    Assignee: Hoffmann-La Roche Inc.
    Inventors: Taishan Hu, Xingchun Han, Buyu Kou, Hong Shen, Shixiang Yan, Zhisen Zhang
  • Patent number: 9888584
    Abstract: A contact pad includes a solder-wettable porous network (310) which wicks the molten solder (130) and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: February 6, 2018
    Assignee: Invensas Corporation
    Inventors: Liang Wang, Rajesh Katkar, Hong Shen, Cyprian Emeka Uzoh
  • Patent number: 9865675
    Abstract: In one embodiment, a method for making a 3D Metal-Insulator-Metal (MIM) capacitor includes providing a substrate having a surface, forming an array of upstanding rods or ridges on the surface, depositing a first layer of an electroconductor on the surface and the array of rods or ridges, coating the first electroconductive layer with a layer of a dielectric, and depositing a second layer of an electroconductor on the dielectric layer. In some embodiments, the array of rods or ridges can be made of a photoresist material, and in others, can comprise bonded wires.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: January 9, 2018
    Assignee: INVENSAS CORPORATION
    Inventors: Liang Wang, Rajesh Katkar, Hong Shen, Cyprian Emeka Uzoh
  • Patent number: 9859234
    Abstract: A method of processing an interconnection element can include providing a substrate element having front and rear opposite surfaces and electrically conductive structure, a first dielectric layer overlying the front surface and a plurality of conductive contacts at a first surface of the first dielectric layer, and a second dielectric layer overlying the rear surface and having a conductive element at a second surface of the second dielectric layer. The method can also include removing a portion of the second dielectric layer so as to reduce the thickness of the portion, and to provide a raised portion of the second dielectric layer having a first thickness and a lowered portion having a second thickness. The first thickness can be greater than the second thickness. At least a portion of the conductive element can be recessed below a height of the first thickness of the second dielectric layer.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: January 2, 2018
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Guilian Gao, Bongsub Lee, Scott McGrath, Hong Shen, Charles G. Woychik, Arkalgud R. Sitaram, Akash Agrawal