Patents by Inventor Hong-Shing Chou

Hong-Shing Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9620326
    Abstract: An apparatus for extending the useful life of an ion source, comprising an arc chamber containing a plurality of cathodes to be used sequentially and a plurality of repellers to protect cathodes when not in use. The arc chamber includes an arc chamber housing defining a reaction cavity, gas injection openings, a plurality of cathodes, and at least one repeller element. A method for extending the useful life of an ion source includes providing power to a first cathode of an arc chamber in an ion source, operating the first cathode, detecting a failure or degradation in performance of the first cathode, energizing a second cathode, and continuing operation of the arc chamber with the second cathode.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: April 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Tsung Lin, Hsiao-Yin Hsieh, Chi-Hao Huang, Hong-Shing Chou, Yeh-Chieh Wang
  • Publication number: 20150130353
    Abstract: An apparatus for extending the useful life of an ion source, comprising an arc chamber containing a plurality of cathodes to be used sequentially and a plurality of repellers to protect cathodes when not in use. The arc chamber includes an arc chamber housing defining a reaction cavity, gas injection openings, a plurality of cathodes, and at least one repeller element. A method for extending the useful life of an ion source includes providing power to a first cathode of an arc chamber in an ion source, operating the first cathode, detecting a failure or degradation in performance of the first cathode, energizing a second cathode, and continuing operation of the arc chamber with the second cathode.
    Type: Application
    Filed: December 22, 2014
    Publication date: May 14, 2015
    Inventors: Chin-Tsung LIN, Hsiao-Yin HSIEH, Chi-Hao HUANG, Hong-Shing CHOU, Yeh-Chieh WANG
  • Patent number: 7175951
    Abstract: A method for in-situ overlay accuracy checking using a first mask having a first pattern and a second mask having a second pattern to expose a layer of photosensitive material formed on a wafer. The first pattern and the second pattern are exposed in the layer of photosensitive material using the first mask, the second mask, and a photolithographic alignment and exposure system. The layer of photosensitive material is then developed and the relative position between the first pattern and the second pattern is analyzed.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: February 13, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Hong-Shing Chou