Abstract: Methods of forming a spin-on-glass (SOG) layer are disclosed. An SOG layer is formed on an integrated circuit substrate. A first curing process is performed on the SOG layer. Less than all of the SOG layer is removed from the integrated circuit substrate through a mask pattern on the SOG layer to provide a remaining portion of the SOG layer on the integrated circuit substrate. A second curing process is performed on the SOG layer. The remaining portion of the SOG layer is removed to expose the integrated circuit substrate.

Abstract: A semiconductor device and manufacturing method thereof include a semiconductor substrate, an interlevel dielectric (ILD) layer formed on the semiconductor substrate, a first contact stud formed in the ILD layer, having a line width of an entrance portion adjacent to the surface of the ILD layer larger than the line width of a contacting portion adjacent to the semiconductor substrate, and a second contact stud spaced apart from the first contact stud and formed in the ILD layer. The semiconductor device further includes a landing pad formed on the ILD layer to contact the surface of the second contact stud, having a line width larger than that of the second contact stud. The second contact stud has a line width of a contacting portion that is the same as that of an entrance portion. Also, at least one spacer comprising an etch stopper material is formed on the sidewalls of the landing pad and the etch stopper is formed on the landing pad.

Abstract: An integrated circuit device is manufactured by forming an insulating layer on a substrate. A capping layer is formed on the insulating layer and both the capping layer and the insulating layer are patterned. Insulating spacers are formed on sidewalls of the insulating layer so that the insulating spacers, the capping layer, and the substrate enclose the insulating layer.

Abstract: An etch-stop layer is selectively provided between layers of a multiple-layered circuit so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying stud so as to serve as an alignment target during formation of an overlying stud formed in an upper layer to be coupled to the underlying stud. In this manner multiple-layered circuits, for example memory devices, can be fabricated in relatively dense configurations.

Abstract: A self aligned contact pad in a semiconductor device and a method for forming the self aligned contact pad are disclosed. A bit line contact pad and a storage node contact pad are simultaneously formed by using a photoresist layer pattern having a T-shaped opening including at least two contact regions. An etch stopping layer is formed over a semiconductor substrate and over a transistor. An interlayer dielectric layer is then formed over the etch stopping layer. Next, the interlayer dielectric layer is planarized to have a planar top surface. A mask pattern having a T-shaped opening is then formed over the interlayer dielectric layer, exposing the active region and a portion of the inactive region. The interlayer dielectric layer and etch stopping layer are sequentially etched to reveal a top surface of the semiconductor substrate using the mask pattern, thereby forming a self aligned contact opening exposing a top surface of the semiconductor substrate. The mask pattern is then removed.