Patents by Inventor Hong-Soo Jeon
Hong-Soo Jeon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240105104Abstract: A pixel includes: a light emitting element; a first transistor including a gate electrode electrically connected to a first node, a second node to which a first power voltage for driving the light emitting element is to be applied, and a third node electrically connected to the light emitting element; and a bias control transistor configured to be controlled in operating timing thereof by a bias control signal, and configured to switch electrical connection between the second node and a bias power line for transmitting a bias voltage. In one frame period, a voltage level of the bias voltage to be applied to the second node sequentially increases.Type: ApplicationFiled: April 12, 2023Publication date: March 28, 2024Inventors: Se Hyuk PARK, Hong Soo KIM, Young Ha SOHN, Jin Wook YANG, Dong Gyu LEE, Jae Hyeon JEON
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Patent number: 10964710Abstract: A non-volatile memory device may include a first semiconductor layer including a peripheral region, the peripheral region including one or more peripheral transistors on a lower substrate. The non-volatile memory device may further include a second semiconductor layer on the peripheral region, the second semiconductor layer including an upper substrate, the second semiconductor layer further including a memory cell array on the upper substrate. The upper substrate may include a first upper substrate on the first semiconductor layer, a first layer on the first upper substrate, and a second upper substrate on the first layer.Type: GrantFiled: January 30, 2020Date of Patent: March 30, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-kil Yun, Chan-ho Kim, Pan-suk Kwak, Hong-soo Jeon
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Publication number: 20200168620Abstract: A non-volatile memory device may include a first semiconductor layer including a peripheral region, the peripheral region including one or more peripheral transistors on a lower substrate. The non-volatile memory device may further include a second semiconductor layer on the peripheral region, the second semiconductor layer including an upper substrate, the second semiconductor layer further including a memory cell array on the upper substrate. The upper substrate may include a first upper substrate on the first semiconductor layer, a first layer on the first upper substrate, and a second upper substrate on the first layer.Type: ApplicationFiled: January 30, 2020Publication date: May 28, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Dong-kil Yun, Chan-ho Kim, Pan-suk Kwak, Hong-soo Jeon
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Patent number: 10559577Abstract: A non-volatile memory device may include a first semiconductor layer including a peripheral region, the peripheral region including one or more peripheral transistors on a lower substrate. The non-volatile memory device may further include a second semiconductor layer on the peripheral region, the second semiconductor layer including an upper substrate, the second semiconductor layer further including a memory cell array on the upper substrate. The upper substrate may include a first upper substrate on the first semiconductor layer, a first layer on the first upper substrate, and a second upper substrate on the first layer.Type: GrantFiled: March 7, 2018Date of Patent: February 11, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-kil Yun, Chan-ho Kim, Pan-suk Kwak, Hong-soo Jeon
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Patent number: 10446575Abstract: A three-dimensional (3D) nonvolatile memory includes a stacked structure that includes a plurality of conductive layers that alternate with and are spaced apart from each other by a plurality of interlayer insulating layers. The stacked structure includes a first cell region, a second cell region spaced apart from the first cell region, and a connection region between the first cell region and the second cell region. The connection region includes a first step portion that contacts the first cell region and has a stepped shape that descends in a direction approaching the second cell region, a second step portion that contacts the second cell region and has a stepped shape that descends in a direction approaching the first cell region, and a connection portion that connects the first cell region and the second cell region.Type: GrantFiled: June 21, 2018Date of Patent: October 15, 2019Assignee: SAMSUNG ELECTRONICS CO., LTDInventors: Chan-Ho Kim, Bong-Soon Lim, Pan-Suk Kwak, Hong-Soo Jeon
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Publication number: 20190139978Abstract: A three-dimensional (3D) nonvolatile memory includes a stacked structure that includes a plurality of conductive layers that alternate with and are spaced apart from each other by a plurality of interlayer insulating layers. The stacked structure includes a first cell region, a second cell region spaced apart from the first cell region, and a connection region between the first cell region and the second cell region. The connection region includes a first step portion that contacts the first cell region and has a stepped shape that descends in a direction approaching the second cell region, a second step portion that contacts the second cell region and has a stepped shape that descends in a direction approaching the first cell region, and a connection portion that connects the first cell region and the second cell region.Type: ApplicationFiled: June 21, 2018Publication date: May 9, 2019Inventors: CHAN-HO KIM, Bong-Soon Lim, Pan-Suk Kwak, Hong-Soo Jeon
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Publication number: 20190067308Abstract: A non-volatile memory device may include a first semiconductor layer including a peripheral region, the peripheral region including one or more peripheral transistors on a lower substrate. The non-volatile memory device may further include a second semiconductor layer on the peripheral region, the second semiconductor layer including an upper substrate, the second semiconductor layer further including a memory cell array on the upper substrate. The upper substrate may include a first upper substrate on the first semiconductor layer, a first layer on the first upper substrate, and a second upper substrate on the first layer.Type: ApplicationFiled: March 7, 2018Publication date: February 28, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Dong-kil YUN, Chan-ho KIM, Pan-suk KWAK, Hong-soo JEON
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Patent number: 7940117Abstract: A voltage generation circuit includes a high voltage detector (HVD), a clock signal control unit (CSCU), an oscillator, a pumping clock control unit (PCCU), and a charge pump. The HVD compares a high voltage applied to a memory cell array with at least one reference voltage to provide at least one comparison signal. The CSCU provides a clock control signal for changing a frequency of a clock signal in response to the at least one comparison signal. The oscillator generates the clock signal having a frequency according to the clock control signal. The PCCU passes or intercepts the clock signal to provide a pumping clock signal, in response to a control signal. The charge pump consecutively performs charge pumping operations to provide the high voltage while the pumping clock signal is applied to the charge pump.Type: GrantFiled: May 13, 2009Date of Patent: May 10, 2011Assignee: Samsung Electronics Co., Ltd.Inventor: Hong-Soo Jeon
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Publication number: 20100232228Abstract: A method of programming a memory device includes comparing a first verify voltage and a distribution voltage of at least one memory cell, and if a result of the comparison is a pass, adjusting the distribution voltage until the distribution voltage is higher than a second verify voltage while comparing the distribution voltage and the second verify voltage.Type: ApplicationFiled: March 2, 2010Publication date: September 16, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hong Soo JEON, Ji-Sang LEE, Oh Suk KWON
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Patent number: 7738309Abstract: A non-volatile semiconductor memory device includes a read voltage generating circuit, a flash cell fuse circuit and a row decoder. The read voltage generating circuit generates a read voltage in response to a read enable signal and a trim code. The flash cell fuse circuit generates the trim code in response to a cell selection signal and a fuse word-line enable signal, the fuse word-line enable signal being activated after the read enable signal by a first delay time. The row decoder decodes the read voltage in response to a row address signal to generate a decoded read voltage, and to provide the decoded read voltage to a memory cell array.Type: GrantFiled: November 28, 2007Date of Patent: June 15, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Hong-Soo Jeon, Dae-Han Kim
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Patent number: 7710788Abstract: A flash memory device includes a flash fuse cell array, a trim code processing unit, a flash memory array, and a regulator. The fuse cell array, which includes multiple nonvolatile fuse cells, is configured to store a first trim code. The trim code processor is configured to generate a second trim code based on the first trim code provided by the fuse cell array and a voltage control code. The flash memory array includes multiple flash memory cells. The regulator is configured to generate a high voltage in response to the second trim code and to provide the high voltage to the flash memory array. The high voltage varies according to erase, program and read operations of the flash memory cells.Type: GrantFiled: October 25, 2007Date of Patent: May 4, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Hong-Soo Jeon, Dae-Han Kim
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Patent number: 7656714Abstract: The NOR flash memory device according to the present invention is operated by a high voltage supplied from bitline selection transistors and includes a bitline bias circuit for supplying a bias voltage of a constant level to the bitline bias transistor. In accordance with the present invention, it is possible to stably supply a desired voltage closing to a power voltage to the bitline bias transistor.Type: GrantFiled: November 2, 2005Date of Patent: February 2, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Hong-Soo Jeon, Seung-Keun Lee
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Publication number: 20090284308Abstract: A voltage generation circuit includes a high voltage detector (HVD), a clock signal control unit (CSCU), an oscillator, a pumping clock control unit (PCCU), and a charge pump. The HVD compares a high voltage applied to a memory cell array with at least one reference voltage to provide at least one comparison signal. The CSCU provides a clock control signal for changing a frequency of a clock signal in response to the at least one comparison signal. The oscillator generates the clock signal having a frequency according to the clock control signal. The PCCU passes or intercepts the clock signal to provide a pumping clock signal, in response to a control signal. The charge pump consecutively performs charge pumping operations to provide the high voltage while the pumping clock signal is applied to the charge pump.Type: ApplicationFiled: May 13, 2009Publication date: November 19, 2009Inventor: Hong-Soo Jeon
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Patent number: 7486573Abstract: A flash memory device may include a memory cell array. The memory cell array may include a plurality of memory cells. The flash memory device may also include a voltage generator which generates a plurality of constant voltages. The voltage generator may comprise of a plurality of voltage regulators, wherein each voltage regulator is configured to divide a high voltage generated from a charge pump to generate at least two constant voltages having a constant voltage difference therebetween. The plurality of voltage regulators may have independent voltage dividing paths, wherein each path is configured to generate a separate constant voltage.Type: GrantFiled: September 14, 2006Date of Patent: February 3, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Hong-Soo Jeon, Dae-Han Kim
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Publication number: 20080158977Abstract: A non-volatile semiconductor memory device includes a read voltage generating circuit, a flash cell fuse circuit and a row decoder. The read voltage generating circuit generates a read voltage in response to a read enable signal and a trim code. The flash cell fuse circuit generates the trim code in response to a cell selection signal and a fuse word-line enable signal, the fuse word-line enable signal being activated after the read enable signal by a first delay time. The row decoder decodes the read voltage in response to a row address signal to generate a decoded read voltage, and to provide the decoded read voltage to a memory cell array.Type: ApplicationFiled: November 28, 2007Publication date: July 3, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hong-Soo Jeon, Dae-Han Kim
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Publication number: 20080117705Abstract: A flash memory device includes a flash fuse cell array, a trim code processing unit, a flash memory array, and a regulator. The fuse cell array, which includes multiple nonvolatile fuse cells, is configured to store a first trim code. The trim code processor is configured to generate a second trim code based on the first trim code provided by the fuse cell array and a voltage control code. The flash memory array includes multiple flash memory cells. The regulator is configured to generate a high voltage in response to the second trim code and to provide the high voltage to the flash memory array. The high voltage varies according to erase, program and read operations of the flash memory cells.Type: ApplicationFiled: October 25, 2007Publication date: May 22, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hong-Soo Jeon, Dae-Han Kim
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Publication number: 20070081391Abstract: A flash memory device may include a memory cell array. The memory cell array may include a plurality of memory cells. The flash memory device may also include a voltage generator which generates a plurality of constant voltages. The voltage generator may comprise of a plurality of voltage regulators, wherein each voltage regulator is configured to divide a high voltage generated from a charge pump to generate at least two constant voltages having a constant voltage difference therebetween. The plurality of voltage regulators may have independent voltage dividing paths, wherein each path is configured to generate a separate constant voltage.Type: ApplicationFiled: September 14, 2006Publication date: April 12, 2007Inventors: Hong-Soo Jeon, Dae-Han Kim
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Publication number: 20060120196Abstract: A trimming circuit may include a plurality of resistors coupled in series between an output node and a reference voltage, and a plurality of transistors. More particularly, each transistor of the plurality of transistors may be electrically coupled in parallel with a respective one of the resistors. Moreover, each of the transistors may include a respective well region, and well regions of different transistors may be isolated. Related memory devices are also discussed.Type: ApplicationFiled: September 30, 2005Publication date: June 8, 2006Inventors: Hong-Soo Jeon, Seung-Keun Lee
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Publication number: 20060092707Abstract: The NOR flash memory device according to the present invention is operated by a high voltage supplied from bitline selection transistors and includes a bitline bias circuit for supplying a bias voltage of a constant level to the bitline bias transistor. In accordance with the present invention, it is possible to stably supply a desired voltage closing to a power voltage to the bitline bias transistor.Type: ApplicationFiled: November 2, 2005Publication date: May 4, 2006Inventors: Hong-Soo Jeon, Seung-Keun Lee