Patents by Inventor Hong-Soo Jeon

Hong-Soo Jeon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10964710
    Abstract: A non-volatile memory device may include a first semiconductor layer including a peripheral region, the peripheral region including one or more peripheral transistors on a lower substrate. The non-volatile memory device may further include a second semiconductor layer on the peripheral region, the second semiconductor layer including an upper substrate, the second semiconductor layer further including a memory cell array on the upper substrate. The upper substrate may include a first upper substrate on the first semiconductor layer, a first layer on the first upper substrate, and a second upper substrate on the first layer.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: March 30, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-kil Yun, Chan-ho Kim, Pan-suk Kwak, Hong-soo Jeon
  • Publication number: 20200168620
    Abstract: A non-volatile memory device may include a first semiconductor layer including a peripheral region, the peripheral region including one or more peripheral transistors on a lower substrate. The non-volatile memory device may further include a second semiconductor layer on the peripheral region, the second semiconductor layer including an upper substrate, the second semiconductor layer further including a memory cell array on the upper substrate. The upper substrate may include a first upper substrate on the first semiconductor layer, a first layer on the first upper substrate, and a second upper substrate on the first layer.
    Type: Application
    Filed: January 30, 2020
    Publication date: May 28, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dong-kil Yun, Chan-ho Kim, Pan-suk Kwak, Hong-soo Jeon
  • Patent number: 10559577
    Abstract: A non-volatile memory device may include a first semiconductor layer including a peripheral region, the peripheral region including one or more peripheral transistors on a lower substrate. The non-volatile memory device may further include a second semiconductor layer on the peripheral region, the second semiconductor layer including an upper substrate, the second semiconductor layer further including a memory cell array on the upper substrate. The upper substrate may include a first upper substrate on the first semiconductor layer, a first layer on the first upper substrate, and a second upper substrate on the first layer.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: February 11, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-kil Yun, Chan-ho Kim, Pan-suk Kwak, Hong-soo Jeon
  • Patent number: 10446575
    Abstract: A three-dimensional (3D) nonvolatile memory includes a stacked structure that includes a plurality of conductive layers that alternate with and are spaced apart from each other by a plurality of interlayer insulating layers. The stacked structure includes a first cell region, a second cell region spaced apart from the first cell region, and a connection region between the first cell region and the second cell region. The connection region includes a first step portion that contacts the first cell region and has a stepped shape that descends in a direction approaching the second cell region, a second step portion that contacts the second cell region and has a stepped shape that descends in a direction approaching the first cell region, and a connection portion that connects the first cell region and the second cell region.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: October 15, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD
    Inventors: Chan-Ho Kim, Bong-Soon Lim, Pan-Suk Kwak, Hong-Soo Jeon
  • Publication number: 20190139978
    Abstract: A three-dimensional (3D) nonvolatile memory includes a stacked structure that includes a plurality of conductive layers that alternate with and are spaced apart from each other by a plurality of interlayer insulating layers. The stacked structure includes a first cell region, a second cell region spaced apart from the first cell region, and a connection region between the first cell region and the second cell region. The connection region includes a first step portion that contacts the first cell region and has a stepped shape that descends in a direction approaching the second cell region, a second step portion that contacts the second cell region and has a stepped shape that descends in a direction approaching the first cell region, and a connection portion that connects the first cell region and the second cell region.
    Type: Application
    Filed: June 21, 2018
    Publication date: May 9, 2019
    Inventors: CHAN-HO KIM, Bong-Soon Lim, Pan-Suk Kwak, Hong-Soo Jeon
  • Publication number: 20190067308
    Abstract: A non-volatile memory device may include a first semiconductor layer including a peripheral region, the peripheral region including one or more peripheral transistors on a lower substrate. The non-volatile memory device may further include a second semiconductor layer on the peripheral region, the second semiconductor layer including an upper substrate, the second semiconductor layer further including a memory cell array on the upper substrate. The upper substrate may include a first upper substrate on the first semiconductor layer, a first layer on the first upper substrate, and a second upper substrate on the first layer.
    Type: Application
    Filed: March 7, 2018
    Publication date: February 28, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dong-kil YUN, Chan-ho KIM, Pan-suk KWAK, Hong-soo JEON
  • Patent number: 7940117
    Abstract: A voltage generation circuit includes a high voltage detector (HVD), a clock signal control unit (CSCU), an oscillator, a pumping clock control unit (PCCU), and a charge pump. The HVD compares a high voltage applied to a memory cell array with at least one reference voltage to provide at least one comparison signal. The CSCU provides a clock control signal for changing a frequency of a clock signal in response to the at least one comparison signal. The oscillator generates the clock signal having a frequency according to the clock control signal. The PCCU passes or intercepts the clock signal to provide a pumping clock signal, in response to a control signal. The charge pump consecutively performs charge pumping operations to provide the high voltage while the pumping clock signal is applied to the charge pump.
    Type: Grant
    Filed: May 13, 2009
    Date of Patent: May 10, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hong-Soo Jeon
  • Publication number: 20100232228
    Abstract: A method of programming a memory device includes comparing a first verify voltage and a distribution voltage of at least one memory cell, and if a result of the comparison is a pass, adjusting the distribution voltage until the distribution voltage is higher than a second verify voltage while comparing the distribution voltage and the second verify voltage.
    Type: Application
    Filed: March 2, 2010
    Publication date: September 16, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong Soo JEON, Ji-Sang LEE, Oh Suk KWON
  • Patent number: 7738309
    Abstract: A non-volatile semiconductor memory device includes a read voltage generating circuit, a flash cell fuse circuit and a row decoder. The read voltage generating circuit generates a read voltage in response to a read enable signal and a trim code. The flash cell fuse circuit generates the trim code in response to a cell selection signal and a fuse word-line enable signal, the fuse word-line enable signal being activated after the read enable signal by a first delay time. The row decoder decodes the read voltage in response to a row address signal to generate a decoded read voltage, and to provide the decoded read voltage to a memory cell array.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: June 15, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Soo Jeon, Dae-Han Kim
  • Patent number: 7710788
    Abstract: A flash memory device includes a flash fuse cell array, a trim code processing unit, a flash memory array, and a regulator. The fuse cell array, which includes multiple nonvolatile fuse cells, is configured to store a first trim code. The trim code processor is configured to generate a second trim code based on the first trim code provided by the fuse cell array and a voltage control code. The flash memory array includes multiple flash memory cells. The regulator is configured to generate a high voltage in response to the second trim code and to provide the high voltage to the flash memory array. The high voltage varies according to erase, program and read operations of the flash memory cells.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: May 4, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Soo Jeon, Dae-Han Kim
  • Patent number: 7656714
    Abstract: The NOR flash memory device according to the present invention is operated by a high voltage supplied from bitline selection transistors and includes a bitline bias circuit for supplying a bias voltage of a constant level to the bitline bias transistor. In accordance with the present invention, it is possible to stably supply a desired voltage closing to a power voltage to the bitline bias transistor.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: February 2, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Soo Jeon, Seung-Keun Lee
  • Publication number: 20090284308
    Abstract: A voltage generation circuit includes a high voltage detector (HVD), a clock signal control unit (CSCU), an oscillator, a pumping clock control unit (PCCU), and a charge pump. The HVD compares a high voltage applied to a memory cell array with at least one reference voltage to provide at least one comparison signal. The CSCU provides a clock control signal for changing a frequency of a clock signal in response to the at least one comparison signal. The oscillator generates the clock signal having a frequency according to the clock control signal. The PCCU passes or intercepts the clock signal to provide a pumping clock signal, in response to a control signal. The charge pump consecutively performs charge pumping operations to provide the high voltage while the pumping clock signal is applied to the charge pump.
    Type: Application
    Filed: May 13, 2009
    Publication date: November 19, 2009
    Inventor: Hong-Soo Jeon
  • Patent number: 7486573
    Abstract: A flash memory device may include a memory cell array. The memory cell array may include a plurality of memory cells. The flash memory device may also include a voltage generator which generates a plurality of constant voltages. The voltage generator may comprise of a plurality of voltage regulators, wherein each voltage regulator is configured to divide a high voltage generated from a charge pump to generate at least two constant voltages having a constant voltage difference therebetween. The plurality of voltage regulators may have independent voltage dividing paths, wherein each path is configured to generate a separate constant voltage.
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: February 3, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Soo Jeon, Dae-Han Kim
  • Publication number: 20080158977
    Abstract: A non-volatile semiconductor memory device includes a read voltage generating circuit, a flash cell fuse circuit and a row decoder. The read voltage generating circuit generates a read voltage in response to a read enable signal and a trim code. The flash cell fuse circuit generates the trim code in response to a cell selection signal and a fuse word-line enable signal, the fuse word-line enable signal being activated after the read enable signal by a first delay time. The row decoder decodes the read voltage in response to a row address signal to generate a decoded read voltage, and to provide the decoded read voltage to a memory cell array.
    Type: Application
    Filed: November 28, 2007
    Publication date: July 3, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-Soo Jeon, Dae-Han Kim
  • Publication number: 20080117705
    Abstract: A flash memory device includes a flash fuse cell array, a trim code processing unit, a flash memory array, and a regulator. The fuse cell array, which includes multiple nonvolatile fuse cells, is configured to store a first trim code. The trim code processor is configured to generate a second trim code based on the first trim code provided by the fuse cell array and a voltage control code. The flash memory array includes multiple flash memory cells. The regulator is configured to generate a high voltage in response to the second trim code and to provide the high voltage to the flash memory array. The high voltage varies according to erase, program and read operations of the flash memory cells.
    Type: Application
    Filed: October 25, 2007
    Publication date: May 22, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-Soo Jeon, Dae-Han Kim
  • Publication number: 20070081391
    Abstract: A flash memory device may include a memory cell array. The memory cell array may include a plurality of memory cells. The flash memory device may also include a voltage generator which generates a plurality of constant voltages. The voltage generator may comprise of a plurality of voltage regulators, wherein each voltage regulator is configured to divide a high voltage generated from a charge pump to generate at least two constant voltages having a constant voltage difference therebetween. The plurality of voltage regulators may have independent voltage dividing paths, wherein each path is configured to generate a separate constant voltage.
    Type: Application
    Filed: September 14, 2006
    Publication date: April 12, 2007
    Inventors: Hong-Soo Jeon, Dae-Han Kim
  • Publication number: 20060120196
    Abstract: A trimming circuit may include a plurality of resistors coupled in series between an output node and a reference voltage, and a plurality of transistors. More particularly, each transistor of the plurality of transistors may be electrically coupled in parallel with a respective one of the resistors. Moreover, each of the transistors may include a respective well region, and well regions of different transistors may be isolated. Related memory devices are also discussed.
    Type: Application
    Filed: September 30, 2005
    Publication date: June 8, 2006
    Inventors: Hong-Soo Jeon, Seung-Keun Lee
  • Publication number: 20060092707
    Abstract: The NOR flash memory device according to the present invention is operated by a high voltage supplied from bitline selection transistors and includes a bitline bias circuit for supplying a bias voltage of a constant level to the bitline bias transistor. In accordance with the present invention, it is possible to stably supply a desired voltage closing to a power voltage to the bitline bias transistor.
    Type: Application
    Filed: November 2, 2005
    Publication date: May 4, 2006
    Inventors: Hong-Soo Jeon, Seung-Keun Lee