Abstract: A microelectronic device package includes a microelectronic device, a masking material defined (MMD) contact, and a non-masking material defined (NMMD) contact. The microelectronic device is supported on, and electrically connected to, one of a package substrate and a redistribution layer. The MMD contact is located in a first region of the one of the package substrate and the redistribution layer and facilitates a first electrical connection between the microelectronic device and the one of the package substrate and the redistribution layer. The NMMD contact is located in a second, different region of the one of the package substrate and the redistribution layer and facilitates a second electrical connection between the microelectronic device and the one of the package substrate and the redistribution layer. Related methods and systems are also disclosed.

Abstract: A semiconductor package having a package substrate including an upper surface, a controller, a first die stack, and a second die stack. The controller, the first die stack, and the second die stack are at the upper surface. The first die stack includes a first shingled sub-stack and a first reverse-shingled sub-stack. The first die stack also includes a first bridging chip between the first shingled and reverse-shingled sub-stacks. The second die stack similarly includes a second shingled sub-stack and a second reverse-shingled sub-stack. The second die stack also includes a second bridging chip bonded to the top of the second reverse-shingled sub-stack. At least a portion of a bottom semiconductor die of the first reverse-shingled sub-stack is vertically aligned with a semiconductor die of the second shingled sub-stack and a semiconductor die of the second reverse-shingled sub-stack.

Abstract: A semiconductor device assembly is provided. The assembly includes a substrate having an upper surface on which is disposed a first device contact, a keep-out region extending from a first side surface of the substrate to a second side surface of the substrate opposite the first, and at least one trace coupled to the first device contact and extending across the keep out region towards a third side surface of the substrate. The assembly further includes at least one semiconductor device disposed over the upper surface of the substrate and coupled to the first device contact. The keep-out region of the substrate is free from conductive structures other than the at least one trace.

Abstract: Some implementations herein provide a semiconductor package and methods of formation. The semiconductor package includes a semiconductor die having a first set of conductive structures connected with a substrate having a second set of conductive structures, where a profile of heights of the second set of conductive structures includes a curvature relative to a surface of the substrate. The curvature is configured to compensate for warpage (e.g., offset warpage) that may be induced to the semiconductor die and/or the substrate during a reflow process that joins the semiconductor die and the substrate. By compensating for the warpage, a planarity of an interface region including solder joints between the first and second sets of conductive structures is increased. Increasing the planarity may reduce solder joint defects in the semiconductor package relative to another semiconductor package including another substrate having conductive structures without the profile having the curvature.

Abstract: A semiconductor device assembly includes a circuit substrate including a first substrate surface and a second substrate surface; a first die stack, a second die stack, and a third die stack arranged on the first substrate surface; a plurality of conductive interconnect structures coupled to the second substrate surface; a first signal channel including a first subset of the plurality conductive interconnect structures; and a second signal channel including a second subset of the plurality conductive interconnect structures. The first signal channel is electrically coupled to a first plurality of die stacks including at least two of the first die stack, the second die stack, and the third die stack. The second signal channel is electrically coupled to a second plurality of die stacks including at least two of the first die stack, the second die stack, and the third die stack.

Abstract: A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.

Abstract: A semiconductor device includes a rigid flex circuit that has a first rigid region and a second rigid region that are electrically connected by a flexible portion. A first die is mounted to a first side of the first rigid region. A second die is mounted to a second side of the second rigid region. The first and second sides are on opposite sides of the rigid flex circuit. The flexible portion is bent to hold the first and second rigid regions in generally vertical alignment with each other.

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, semiconductor device assembly includes a first redistribution layer and a second redistribution layer, a first semiconductor die disposed between the first redistribution layer and the second redistribution layer and connected to the first redistribution layer, and a second semiconductor die disposed between the first redistribution layer and the second redistribution layer and connected to the second redistribution layer. The first semiconductor die may have an active surface and a back surface opposite the active surface of the first semiconductor die. The second semiconductor die may have an active surface and a back surface opposite the active surface of the second semiconductor die. The second semiconductor die may be stacked on the first semiconductor die with the back surface of the second semiconductor die facing the back surface of the first semiconductor die.

Abstract: Techniques are disclosed for the use of fused vector processor instructions by a vector processor architecture. Each fused vector processor instruction may include a set of fields associated with individual vector processing instructions. The vector processor architecture may implement local buffers facilitating a single vector processor instruction to be used to execute each of the individual vector processing instructions without re-accessing vector registers between each executed individual vector processing instruction. The vector processor architecture enables less communication across the interconnection network, thereby increasing interconnection network bandwidth and the speed of computations, and decreasing power usage.

Abstract: Implementations described herein relate to techniques and apparatuses related to a structure that may be used for characterizing properties related to an interfacial adhesion strength between an epoxy mold compound and a vertical edge of a semiconductor die included in a semiconductor die package. The techniques and apparatuses may be used to provide a more comprehensive understanding of interfacial adhesion strengths within the semiconductor die package relative to techniques available in semiconductor industry standards.

Abstract: Semiconductor devices having three-dimensional bonding schemes and associated systems and methods are disclosed herein. In some embodiments, the semiconductor device includes a package substrate, a stack of semiconductor dies carried by the package substrate, and an interconnect module carried by the package substrate adjacent the stack of semiconductor dies. The stack of semiconductor dies can include a first die carried by the package substrate and a second die carried by the first die. Meanwhile, the interconnect module can include at least a first tier and a second tier. The first tier can be carried by and electrically coupled to the package substrate, and the second tier can be carried by and electrically coupled to the first tier. In turn, the second die can be electrically coupled to the second tier.

Abstract: Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to corresponding to first and second distances between electrical contacts of the first and second surface-mount capacitors.

Abstract: A semiconductor package including a package substrate with an upper surface, a controller, and a die stack. The controller and the die stack are at the upper surface. The die stack includes a shingled sub-stack of semiconductor dies, a reverse-shingled sub-stack of semiconductor dies, and a bridging chip. The bridging chip is bonded between the shingled sub-stack and the reverse-shingled sub-stack, and has an internal trace. A first wire segment is bonded between the controller and a first end of the bridging chip, and a second wire segment is bonded between a second end of the bridging chip and each semiconductor die of the shingled sub-stack. The internal trace electrically couples the first and second wire segments. Additionally, a third wire segment is bonded between the controller and each semiconductor die of the reverse-shingled sub-stack.

Abstract: An apparatus includes selectable a circuit placement mechanism configured to support two or more different circuit layouts. The circuit placement mechanism may include an overlap of electrical connections associated with the two or more circuit layouts and joined through an etch back selector. The etch back selector may enable the apparatus to function according to a selected one of the two or more different circuit layouts.

Abstract: Semiconductor devices having three-dimensional bonding schemes and associated systems and methods are disclosed herein. In some embodiments, the semiconductor device includes a package substrate, a stack of semiconductor dies carried by the package substrate, and an interconnect module carried by the package substrate adjacent the stack of semiconductor dies. The stack of semiconductor dies can include a first die carried by the package substrate and a second die carried by the first die. Meanwhile, the interconnect module can include at least a first tier and a second tier. The first tier can be carried by and electrically coupled to the package substrate, and the second tier can be carried by and electrically coupled to the first tier. In turn, the second die can be electrically coupled to the second tier.

Abstract: The present disclosure features signal-regulatory protein ? (SIRP-?) polypeptides and constructs that are useful, e.g., to target a cell (e.g., a cancer cell or a cell of the immune system), to increase phagocytosis of the target cell, to eliminate immune cells such as regulatory T-cells, to kill cancer cells, to treat a disease (e.g., cancer) in a subject, or any combinations thereof. The SIRP-? constructs include a high affinity SIRP-? D1 domain or variant thereof that binds CD47 with higher affinity than a wild-type SIRP-?. The SIRP-? polypeptides or constructs include a SIRP-? D1 variant fused to an Fc domain monomer, a human serum albumin (HSA), an albumin-binding peptide, or a polyethylene glycol (PEG) polymer. Compositions provided herein include (i) a polypeptide including a signal-regulatory protein ? (SIRP-?) D1 variant and (ii) an antibody.

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly includes a circuit substrate comprising a first substrate surface and a second substrate surface arranged opposite to the first substrate surface; at least one die arranged on the first substrate surface; a package casing disposed over the first substrate surface, wherein the package casing encapsulates the at least one die and covers at least part of the first substrate surface; a plurality of conductive interconnect structures coupled to the second substrate surface, wherein the plurality of conductive interconnect structures are electrically coupled to the at least one die via the circuit substrate; and at least one molded compound structure arranged on the second substrate surface, wherein the at least one molded compound structure is configured to reduce a coplanarity of the plurality of conductive interconnect structures.

Abstract: Provided are methods of treating cancer that comprise administering a polypeptide (e.g. a fusion polypeptide) that comprises a SIRP? D1 domain variant and an Fc domain variant in combination with at least one chemotherapy agent and/or at least one therapeutic antibody. Also provided are related kits.

Abstract: At least one embodiment of a semiconductor device assembly include a cross-stack substrate can comprise an assembly substrate including an upper surface, a first and second die stack at the upper surface, and a cross-stack substrate spaced from the upper surface. The first and second die stacks can each include multiple semiconductor dies in electric communication with the assembly substrate, and the cross-stack substrate can be coupled to and extending between a first and a second semiconductor die of the first and second die stacks, respectively. A passive semiconductor component can be carried by the cross-stack substrate, and can be in electric communication with the assembly substrate. Further, the passive semiconductor component can be in electric communication with the first semiconductor die of the first die stack exclusively via the assembly substrate.

Abstract: A microelectronic device includes a controller device, a first die vertically overlying the controller device, a second die vertically overlying the first die, and a wire. The first die includes a first pad horizontally separated from a horizontal center of the controller device by a first distance. The second die includes a second pad horizontally separated from the horizontal center of the controller device by a second distance larger than the first distance. The wire contacts the first pad of the first die and the second pad of the second die. Memory device packages and electronic systems are also disclosed.