Patents by Inventor Hong-Wei Chan
Hong-Wei Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923295Abstract: A semiconductor structure includes a first dielectric layer over a first conductive line and a second conductive line, a high resistance layer over a portion of the first dielectric layer, a second dielectric layer on the high resistance layer, a low-k dielectric layer over the second dielectric layer, a first conductive via extending through the low-k dielectric layer and the second dielectric layer, and a second conductive via extending through the low-k dielectric layer and the first dielectric layer to the first conductive line. The first conductive via extends into the high resistance layer.Type: GrantFiled: June 19, 2020Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hong-Wei Chan, Yung-Shih Cheng, Wen-Sheh Huang, Yu-Hsiang Chen
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Patent number: 11908829Abstract: In an embodiment, a method includes performing a first plasma deposition to form a buffer layer over a first side of a first integrated circuit device, the first integrated circuit device comprising a first substrate and a first interconnect structure; performing a second plasma deposition to form a first bonding layer over the buffer layer, wherein a plasma power applied during the second plasma deposition is greater than a plasma power applied during the first plasma deposition; planarizing the first bonding layer; forming a second bonding layer over a second substrate; pressing the second bonding layer onto the first bonding layer; and removing the first substrate.Type: GrantFiled: June 17, 2021Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yao-Te Huang, Hong-Wei Chan, Yung-Shih Cheng
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Publication number: 20230369285Abstract: A method of fabricating a semiconductor chip includes the following steps. A bonding material layer is formed on a first wafer substrate and is patterned to form a first bonding layer having a strength adjustment pattern. A semiconductor component layer and a first interconnect structure layer are formed on a second wafer substrate. The first interconnect structure layer is located. A second bonding layer is formed on the first interconnect structure layer. The second wafer substrate is bonded to the first wafer substrate by contacting the second bonding layer with the first bonding layer. A bonding interface of the second bonding layer and the first bonding layer is smaller than an area of the second bonding layer. A second interconnect structure layer is formed on the semiconductor component layer. A conductor terminal is formed on the second interconnect structure layer.Type: ApplicationFiled: July 26, 2023Publication date: November 16, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Wei Chan, Jiing-Feng Yang, Yung-Shih Cheng, Yao-Te Huang, Hui Lee
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Patent number: 11756924Abstract: A method of fabricating a semiconductor chip includes the following steps. A bonding material layer is formed on a first wafer substrate and is patterned to form a first bonding layer having a strength adjustment pattern. A semiconductor component layer and a first interconnect structure layer are formed on a second wafer substrate. The first interconnect structure layer is located. A second bonding layer is formed on the first interconnect structure layer. The second wafer substrate is bonded to the first wafer substrate by contacting the second bonding layer with the first bonding layer. A bonding interface of the second bonding layer and the first bonding layer is smaller than an area of the second bonding layer. A second interconnect structure layer is formed on the semiconductor component layer. A conductor terminal is formed on the second interconnect structure layer.Type: GrantFiled: March 25, 2021Date of Patent: September 12, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Wei Chan, Jiing-Feng Yang, Yung-Shih Cheng, Yao-Te Huang, Hui Lee
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Publication number: 20220359387Abstract: A method of forming a semiconductor device includes forming a conductive feature and a first punch stop layer, where the conductive feature has a first top surface, and where the first punch stop layer has a second top surface that is substantially level with the first top surface. The method further includes forming a resistive element over the first punch stop layer. The method further includes etching through a first portion of the resistive element to form a first trench that exposes both the second top surface of the first punch stop layer and a first sidewall surface of the resistive element. The method further includes forming a first conductive via within the first trench, where the first conductive via contacts the first sidewall surface of the resistive element.Type: ApplicationFiled: July 20, 2022Publication date: November 10, 2022Inventors: Hong-Wei CHAN, Yung-Shih CHENG, Wen-Sheh HUANG
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Publication number: 20220336583Abstract: A method includes forming a transistor over a front side of a substrate; forming a front-side interconnect structure over the transistor, the front-side interconnect structure comprising layers of conductive lines, and conductive vias interconnecting the layers of conductive lines; forming a first bonding layer over the front-side interconnect structure; forming a second bonding layer over a carrier substrate; bonding the front-side interconnect structure to the carrier substrate by pressing the first bonding layer against the second bonding layer; and forming a backside interconnect structure over a backside of the substrate after bonding the front-side interconnect structure to the carrier substrate.Type: ApplicationFiled: September 20, 2021Publication date: October 20, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Guan-Yao TU, Su-Jen SUNG, Tze-Liang LEE, Hong-Wei CHAN
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Publication number: 20220310527Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming an interconnect structure over a device wafer. The device wafer includes a first integrated circuit, a semiconductor substrate, and a redistribution structure. The method further includes forming a metallization layer and a group of dummy insertion structures having a stepped pattern density in a topmost dielectric layer of the interconnect structure. The group of dummy insertion structures and the metallization layer are planarized with the dielectric layer. The method further includes forming a first bonding layer over the group of dummy insertion structures, the metallization layer, and the dielectric layer. The method further includes bonding a carrier wafer to the first bonding layer, forming an opening through the semiconductor substrate, and forming a conductive via in the opening and electrically coupled to the redistribution structure.Type: ApplicationFiled: July 30, 2021Publication date: September 29, 2022Inventors: Yao-Te Huang, Hong-Wei Chan, Yung-Shih Cheng, Jiing-Feng Yang, Hui Lee
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Publication number: 20220310559Abstract: A method of fabricating a semiconductor chip includes the following steps. A bonding material layer is formed on a first wafer substrate and is patterned to form a first bonding layer having a strength adjustment pattern. A semiconductor component layer and a first interconnect structure layer are formed on a second wafer substrate. The first interconnect structure layer is located. A second bonding layer is formed on the first interconnect structure layer. The second wafer substrate is bonded to the first wafer substrate by contacting the second bonding layer with the first bonding layer. A bonding interface of the second bonding layer and the first bonding layer is smaller than an area of the second bonding layer. A second interconnect structure layer is formed on the semiconductor component layer. A conductor terminal is formed on the second interconnect structure layer.Type: ApplicationFiled: March 25, 2021Publication date: September 29, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Wei Chan, Jiing-Feng Yang, Yung-Shih Cheng, Yao-Te Huang, Hui Lee
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Publication number: 20220310556Abstract: In an embodiment, a method includes performing a first plasma deposition to form a buffer layer over a first side of a first integrated circuit device, the first integrated circuit device comprising a first substrate and a first interconnect structure; performing a second plasma deposition to form a first bonding layer over the buffer layer, wherein a plasma power applied during the second plasma deposition is greater than a plasma power applied during the first plasma deposition; planarizing the first bonding layer; forming a second bonding layer over a second substrate; pressing the second bonding layer onto the first bonding layer; and removing the first substrate.Type: ApplicationFiled: June 17, 2021Publication date: September 29, 2022Inventors: Yao-Te Huang, Hong-Wei Chan, Yung-Shih Cheng
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Patent number: 11437313Abstract: A method of forming a semiconductor device includes forming a conductive feature and a first punch stop layer, where the conductive feature has a first top surface, and where the first punch stop layer has a second top surface that is substantially level with the first top surface. The method further includes forming a resistive element over the first punch stop layer. The method further includes etching through a first portion of the resistive element to form a first trench that exposes both the second top surface of the first punch stop layer and a first sidewall surface of the resistive element. The method further includes forming a first conductive via within the first trench, where the first conductive via contacts the first sidewall surface of the resistive element.Type: GrantFiled: December 3, 2020Date of Patent: September 6, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hong-Wei Chan, Yung-Shih Cheng, Wen-Sheh Huang
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Publication number: 20210257296Abstract: A method of forming a semiconductor device includes forming a conductive feature and a first punch stop layer, where the conductive feature has a first top surface, and where the first punch stop layer has a second top surface that is substantially level with the first top surface. The method further includes forming a resistive element over the first punch stop layer. The method further includes etching through a first portion of the resistive element to form a first trench that exposes both the second top surface of the first punch stop layer and a first sidewall surface of the resistive element. The method further includes forming a first conductive via within the first trench, where the first conductive via contacts the first sidewall surface of the resistive element.Type: ApplicationFiled: December 3, 2020Publication date: August 19, 2021Inventors: Hong-Wei CHAN, Yung-Shih CHENG, Wen-Sheh HUANG
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Publication number: 20210257295Abstract: A semiconductor structure includes a first dielectric layer over a first conductive line and a second conductive line, a high resistance layer over a portion of the first dielectric layer, a low-k dielectric layer over the second dielectric layer, a second dielectric layer on the high resistance layer, a first conductive via extending through the low-k dielectric layer and the second dielectric layer, and a second conductive via extending through the low-k dielectric layer and the first dielectric layer to the first conductive line. The first conductive via extends into the high resistance layer.Type: ApplicationFiled: June 19, 2020Publication date: August 19, 2021Inventors: Hong-Wei Chan, Yung-Shih Cheng, Wen-Sheh Huang, Yu-Hsiang Chen