Abstract: The invention discloses DC-DC converters comprising an inductance, a pulse width modulator generating a pulse signal according to the voltage level of a transformed voltage output terminal, a load sensor sensing a load current, an adaptive enable signal generator generating a PMOS transistor enable signal and an NMOS transistor enable signal based on the pulse signal and the load current, and a power transistor set comprising at least one PMOS transistor and an NMOS transistor. The power transistor set is used in coupling the transformed voltage output terminal to an original DC voltage source or ground via the inductance. The conductance of the PMOS and NMOS transistors are controlled by the PMOS and NMOS transistor enable signals, respectively. The adaptive enable signal generator makes a first dead-time between the PMOS and NMOS transistor enable signals decreasing with increasing load current.

Abstract: A power supply apparatus for supplying an output voltage to a load is provided, which comprises a power output unit, a feedback unit and a control unit. The power output unit adjusts and supplies the output voltage to the load in accordance with at least one driving signal. The feedback unit dynamically detects output condition of the power output unit and outputs the corresponding detection result. The control unit determines a skipping ratio for an internal clock in accordance with the detection result output from the feedback unit, and outputs the internal clock with a part of the pulses being skipped to act as the driving signal.

Abstract: A power supply apparatus for supplying an output voltage to a load is provided, which comprises a power output unit, a feedback unit and a control unit. The power output unit adjusts and supplies the output voltage to the load in accordance with at least one driving signal. The feedback unit dynamically detects output condition of the power output unit and outputs the corresponding detection result. The control unit determines a skipping ratio for an internal clock in accordance with the detection result output from the feedback unit, and outputs the internal clock with a part of the pulses being skipped to act as the driving signal.

Abstract: A delay line, an analog-to-digital converting device and a load-sensing circuit using the same are provided. The delay line comprises a delay-control terminal, a reset terminal, and n delay cells DCELLx (0<x?n). The delay cells DCELL1˜DCELLn are connected in series to each other. Each of the delay cells DCELLx is coupled to the delay-control terminal and the reset terminal for transmitting the first level stage by stage between the delay cells according to a delay time decided by the delay-control terminal in a sensing period. The outputs of all delay cells are reset to the second level when the sensing period is finished. The sensing period is decided by the signal from the reset terminal. Wherein, at least an output terminal ty (0<y?n) of a delay cell DCELLy among the delay cells DCELL1˜DCELLn used as output terminal of the delay line.

Abstract: A delay line, an analog-to-digital converting device and a load-sensing circuit using the same are provided. The delay line comprises a delay-control terminal, a reset terminal, n delay cells DCELLx (0<x?n). The delay cells DCELL1˜DCELLn are connected in series to each other. Each of the delay cells DCELLx is coupled to the delay-control terminal and the reset terminal for transmitting the first level stage by stage between the delay cells according to a delay time decided by the delay-control terminal in a sensing period. The outputs of all delay cells are reset to the second level when the sensing period is finished. The sensing period is decided by the signal from the reset terminal. Wherein, at least an Output tenninal ty (0<y?n) of a delay cell DCELLy among the delay cells DCELL1˜DCELLn used as output terminal of the delay line.

Abstract: A DC-DC converter includes an error amplifier that includes an operational transconductance amplifier (OTA), a compensation circuit, and a fast transient controller. The OTA includes a compensation resistor, a compensation capacitor of Cz, and a Miller circuit. The equalization capacitance generated by the compensation capacitor and the Miller circuit is (1+k) Cz. The Miller circuit includes three transistors operated in the triode region. The ratio of the current through the transistors is 1:mk:(1?m)k. The current through the compensation capacitor in a second mode is (1+mk) times that in a first mode. The fast transient controller switches the Miller circuit between the first and second modes according to a feedback voltage dependent on the output voltage of the DC-DC converter.