Patents by Inventor Hong-Wen Lee

Hong-Wen Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230023998
    Abstract: An electrical connector assembly including a first connector and a second connector to be mated with each other is provided. The first connector includes a first body, and at least one first terminal and multiple second terminals disposed therein. The second terminals are symmetrically arranged at opposite sides of the first terminal. The second connector includes a second body, at least one third terminal movably disposed in the second body, multiple fourth terminals disposed in the second body and symmetrically arranged at opposite sides of the third terminal, and a driving module electrically connected to at least one of the fourth terminals and structurally connected to the third terminal. In the mating process of the first and second connector, the second terminals and the fourth terminals are electrically connected firstly, to trigger the driving module to move the third terminal to be structurally and electrically connected to the first terminal.
    Type: Application
    Filed: June 29, 2022
    Publication date: January 26, 2023
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Chun-Cheng Lin, Shy-Luen Chern, Chih-Hsiang Tang, Hong-Wen Lee
  • Publication number: 20100213649
    Abstract: A shock absorber and an assembling method of an electronic device using the same are provided. The shock absorber includes a first connecting portion, a second connecting portion and a number of elastic arms. The two connecting portions respectively connect to a housing and a circuit board of the electronic device. Two ends of each elastic arm are respectively connected to the two connecting portions to buffer the relative movement between the housing and the circuit board. The method includes the following steps. First, the shock absorber including the first connecting portion, the second connecting portion and the elastic arms is provided. Then the second connecting portion is connected to a surface of the circuit board surrounding a through hole of the circuit board. After connecting the second connecting portion, the housing is connected to the first connecting portion.
    Type: Application
    Filed: May 27, 2009
    Publication date: August 26, 2010
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Hong Wen Lee, Yi Ming Chang
  • Patent number: 7713855
    Abstract: A method for forming a bit-line contact plug includes providing a substrate including a transistor which includes a gate structure and a source/drain at both sides of the gate structure; forming a conductive layer, a bit-line contact material layer and a hard mask layer; performing an etching process using the conductive layer as an etching stop layer to etch the bit-line contact material layer and the hard mask layer and forming the bit-line contact plug on the source/drain. A transistor structure includes a gate structure and a source/drain at both sides of the gate structure, a conductive layer covering part of the gate structure and connected to the source/drain, and a bit-line contact plug disposed on the conductive layer and directly connected to the conductive layer.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: May 11, 2010
    Assignee: Nanya Technology Corp.
    Inventors: Yu-Chung Fang, Hong-Wen Lee, Kuo-Chung Chen, Jen-Jui Huang, Jing-Kae Liou
  • Publication number: 20090061588
    Abstract: A method for fabricating a dynamic random access memory is provided. A substrate having two trench capacitors therein is provided, an isolation structure protruding from a surface of the substrate is formed on each trench capacitor, a spacer is formed on the substrate at two sides of each of the isolation structures, and a block layer is formed between each spacer and each isolation structure and between each spacer and the substrate. A trench is formed in the substrate between the trench capacitors, and partial of the trench is located under partial of the spacers and partial of the block layer. The spacers, the block layer, and partial of the isolation structures above the trench are removed. A gate structure protruding from the surface of the substrate is formed in the trench. A doped region is formed in the substrate at each of two sides of the gate structure.
    Type: Application
    Filed: January 7, 2008
    Publication date: March 5, 2009
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Chang-Ho Yeh, Hong-Wen Lee
  • Publication number: 20080303103
    Abstract: The present invention provides a semiconductor structure and a method of forming the same. The method includes the steps of providing a substrate, forming a mask layer with an opening on the substrate, locally oxidizing the substrate to form an oxide layer within the opening, removing the oxide layer, such that a partial surface of the substrate becomes a curve surface, forming a sacrificial layer on the curve surface, forming a first doped region in the substrate and under the hard mask layer, forming a gate stack within the opening, removing the hard mask layer, forming a spacer on a sidewall of the gate stack, and forming a second doped region in the substrate and under the spacer. The second doped region has a dopant concentration is larger than that of the first doped region. Therefore, the oxide layer increases the surface area of the substrate so as to increase the channel length. Thus, the leakage between the source region and the drain region can be improved.
    Type: Application
    Filed: October 31, 2007
    Publication date: December 11, 2008
    Applicant: NANYA TECHNOLOGY CORP.
    Inventors: Kuo Chung CHEN, Jen-Jui HUANG, Hong Wen LEE
  • Publication number: 20080268640
    Abstract: A method for forming a bit-line contact plug includes providing a substrate including a transistor which includes a gate structure and a source/drain at both sides of the gate structure; forming a conductive layer, a bit-line contact material layer and a hard mask layer; performing an etching process using the conductive layer as an etching stop layer to etch the bit-line contact material layer and the hard mask layer and forming the bit-line contact plug on the source/drain. A transistor structure includes a gate structure and a source/drain at both sides of the gate structure, a conductive layer covering part of the gate structure and connected to the source/drain, and a bit-line contact plug disposed on the conductive layer and directly connected to the conductive layer.
    Type: Application
    Filed: July 20, 2007
    Publication date: October 30, 2008
    Inventors: Yu-Chung Fang, Hong-Wen Lee, Kuo-Chung Chen, Jen-Jui Huang, Jing-Kae Liou
  • Patent number: 7170740
    Abstract: A foldable support structure suitable for a notebook is provided. The notebook includes a keyboard, a circuit board, and a support frame, disposed above the circuit board for carrying the edge of the keyboard. The support structure is disposed inside an opening of the support frame for supporting the bottom of the keyboard. The support structure and the support frame are fabricated as a whole. The support structure includes a flexibility section, a support section and a pedestal section. The flexibility section is connected to the support frame and the support section. The pedestal section is connected to the support section. The deformed flexibility section keeps the support section away from the circuit board. The support section has a support surface for supporting the keyboard. The pedestal section is suitable for connecting the circuit board such that a distance is kept between the support section and the circuit board.
    Type: Grant
    Filed: January 19, 2006
    Date of Patent: January 30, 2007
    Assignee: Compal Electronics, Inc.
    Inventors: Jen-Hao Liu, San-Yang Lo, Hong-Wen Lee