Patents by Inventor Hong Xiao
Hong Xiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11968832Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the disclosed method comprises forming a plurality of dielectric stacks stacked on one another over a substrate to create a multiple-stack staircase structure. Each one of the plurality of dielectric stacks comprises a plurality of dielectric pairs arranged along a direction perpendicular to a top surface of the substrate. The method further comprises forming a filling structure that surrounds the multiple-stack staircase structure, forming a semiconductor channel extending through the multiple-staircase structure, wherein the semiconductor channel comprises unaligned sidewall surfaces, and forming a supporting pillar extending through at least one of the multiple-staircase structure and the filling structure, wherein the supporting pillar comprises aligned sidewall surfaces.Type: GrantFiled: October 16, 2020Date of Patent: April 23, 2024Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Jun Liu, Zongliang Huo, Li Hong Xiao, Zhenyu Lu, Qian Tao, Yushi Hu, Sizhe Li, Zhao Hui Tang, Yu Ting Zhou, Zhaosong Li
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Patent number: 11948489Abstract: A display panel, a display device and a driving method. The display panel includes a display region and a peripheral region. The display region includes a subpixel unit array having a plurality of rows and a plurality of columns of subpixel units, and the peripheral region includes a gate drive circuit. The display region further includes a plurality of gate lines and a plurality of data lines. The gate drive circuit comprises a plurality of shift register units, and the plurality of gate lines are electrically connected with the plurality of shift register units. The gate drive circuit comprises two shift-register-unit scanning groups, in the shift-register-unit scanning groups, a (k+1)th shift register unit and a (k)th shift register unit form one shift register unit group.Type: GrantFiled: April 20, 2023Date of Patent: April 2, 2024Assignees: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Zhaohui Meng, Wei Sun, Wenchao Han, Hong Yang, Lin Cong, Wenjun Xiao
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Patent number: 11943923Abstract: Embodiments of methods to form three-dimensional (3D) memory devices include the following operations. First, an initial channel hole is formed in a stack structure of a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. An offset is formed between a side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers on a sidewall of the initial channel hole to form a channel hole. A semiconductor channel is formed by filling the channel hole with a channel-forming structure, the semiconductor channel having a memory layer including a plurality of first memory portions each surrounding a bottom of a respective second layer and a plurality of second memory portions each connecting adjacent first memory portions.Type: GrantFiled: August 14, 2019Date of Patent: March 26, 2024Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventor: Li Hong Xiao
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Patent number: 11943928Abstract: Embodiments of a channel hole plug structure of 3D memory devices and fabricating methods thereof are disclosed. The memory device includes an alternating layer stack disposed on a substrate, an insulating layer disposed on the alternating dielectric stack, a channel hole extending vertically through the alternating dielectric stack and the insulating layer, a channel structure including a channel layer in the channel hole, and a channel hole plug in the insulating layer and above the channel structure. The channel hole plug is electrically connected with the channel layer. A projection of the channel hole plug in a lateral plane covers a projection of the channel hole in the lateral plane.Type: GrantFiled: April 19, 2022Date of Patent: March 26, 2024Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Li Hong Xiao, Zhenyu Lu, Qian Tao, Yushi Hu, Jun Chen, LongDong Liu, Meng Wang
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Publication number: 20240090223Abstract: A 3D-NAND memory device is provided. The memory device includes a substrate, a bottom select gate (BSG) disposed over the substrate, a plurality of word lines positioned over the BSG with a staircase configuration and a plurality of insulating layers disposed between the substrate, the BSG, and the plurality of word lines. In the disclosed memory device, one or more first dielectric trenches are formed in the BSG and extend in a length direction of the substrate to separate the BSG into a plurality of sub-BSGs. In addition, one or more common source regions are formed over the substrate and extend in the length direction of the substrate. The one or more common source regions further extend through the BSG, the plurality of word lines and the plurality of insulating layers.Type: ApplicationFiled: November 13, 2023Publication date: March 14, 2024Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Yali SONG, Li Hong XIAO, Ming WANG
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Patent number: 11914290Abstract: A device area includes at least a first layer of photoresist and a second layer of photoresist. First layer metrology targets are positioned at an edge of one of the sides of the first layer of the mat. The first layer metrology targets have a relaxed pitch less than a device pitch. Secondary electron and back-scattered electron images can be simultaneously obtained.Type: GrantFiled: July 20, 2020Date of Patent: February 27, 2024Assignee: KLA CORPORATIONInventor: Hong Xiao
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Patent number: 11889686Abstract: Aspects of the disclosure provide a method for fabricating semiconductor device. The method includes characterizing an etch process that is used to etch channel holes and dummy channel holes in a stack of alternating sacrificial gate layers and insulating layers upon a substrate of a semiconductor device. The channel holes are in a core region and the dummy channel holes are in a staircase region. The stack of alternating sacrificial gate layers and insulating layers extend from the core region into in the staircase region of a stair-step form. The method further includes determining a first shape for defining the dummy channel holes in a layout based on the characterization of the etch process. The first shape is different from a second shape for defining the channel holes.Type: GrantFiled: September 7, 2021Date of Patent: January 30, 2024Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Miao Shen, Li Hong Xiao, Yushi Hu, Qian Tao, Mei Lan Guo, Yong Zhang, Jian Hua Sun
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Patent number: 11856776Abstract: A method of forming a structure of 3D NAND memory device, including steps of forming a first stack layer on a substrate, forming a first channel hole extending through the first stack layer, forming a block layer on a surface of the first stack layer and the first channel hole, forming a sacrificial layer in the first channel hole, forming a second stack layer on the first stack layer and the sacrificial layer, performing a first etch process to form a second channel hole extending through the second stack layer and at least partially overlapping the first channel hole and to remove the sacrificial layer in the first channel hole, removing the block layer exposed from the second channel hole, and forming a function layer on a surface of the first channel hole and the second channel hole.Type: GrantFiled: September 28, 2021Date of Patent: December 26, 2023Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Li Hong Xiao, Li Xun Gu
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Memory stacks having silicon nitride gate-to-gate dielectric layers and methods for forming the same
Patent number: 11849582Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. a memory stack including a plurality of interleaved gate conductive layers and gate-to-gate dielectric layers above a substrate is formed. Each of the gate-to-gate dielectric layers includes a silicon nitride layer. A NAND memory string extending vertically through the interleaved gate conductive layers and gate-to-gate dielectric layers of the memory stack is formed. A slit structure extending vertically through the interleaved gate conductive layers and gate-to-gate dielectric layers of the memory stack is formed.Type: GrantFiled: November 21, 2020Date of Patent: December 19, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventor: Li Hong Xiao -
Patent number: 11844216Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming an alternating layer stack on a substrate; forming a plurality of channel holes in the alternating layer stack, each penetrating vertically through the alternating layer stack; forming a functional layer including a storage layer on a sidewall of each channel hole, wherein the storage layer has an uneven surface; forming a channel layer to cover the functional layer in each channel hole; and forming a filling structure to cover the channel layer and fill each channel hole.Type: GrantFiled: August 6, 2021Date of Patent: December 12, 2023Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Li Hong Xiao, Jun Liu
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Patent number: 11825656Abstract: In a method for manufacturing a memory device, a plurality of first insulating layers and a bottom select gate (BSG) layer are formed over a substrate, where the first insulating layers are disposed between the substrate and the BSG layer. One or more first dielectric trenches are formed to pass through the BSG layer and the first insulating layers, and extend in a length direction of the substrate. A plurality of word line layers and a plurality of second insulating layers are formed over the BSG layer, where the second insulating layers are disposed between the BSG layer and the word line layers. One or more common source regions are formed over the substrate to extend in the length direction of the substrate, and further extend through the BSG layer, the first insulating layers, the word line layers, and the second insulating layers.Type: GrantFiled: June 30, 2022Date of Patent: November 21, 2023Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Yali Song, Li Hong Xiao, Ming Wang
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Patent number: 11800710Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming a plurality of hybrid shallow trench isolation structures in a substrate, each hybrid shallow trench isolation structure comprising a dielectric sublayer and a conductive sublayer, both of which are embedded in the substrate; forming an alternating dielectric stack on the substrate; forming a slit penetrating vertically through the alternating dielectric stack and extending in a horizontal direction to expose a row of hybrid shallow trench isolation structures; forming a plurality of array common source contacts in the slit, each array common source contact being in electric contact with a corresponding hybrid shallow trench isolation structure.Type: GrantFiled: February 12, 2021Date of Patent: October 24, 2023Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Li Hong Xiao, Zongliang Huo
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Patent number: 11758722Abstract: Embodiments of 3D memory devices and the fabrication methods to form the 3D memory devices are provided. A 3D memory device includes a substrate, a memory deck, and a memory string. The memory deck includes a plurality of interleaved conductor layers and dielectric layers on the substrate. The memory string extends vertically through the memory deck. A bottom conductor layer of the plurality of interleaved conductor layers and dielectric layers can intersect with and contact the memory string.Type: GrantFiled: June 27, 2019Date of Patent: September 12, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventor: Li Hong Xiao
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Patent number: 11758731Abstract: A three-dimensional (3D) memory device includes a peripheral device, a plurality of memory strings, a layer between the peripheral device and the plurality of memory strings, and a contact. The layer includes a conduction region and an isolation region. The contact extends through the isolation region of the layer.Type: GrantFiled: May 17, 2021Date of Patent: September 12, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Zongliang Huo, Zhiliang Xia, Li Hong Xiao, Jun Chen
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Patent number: 11758729Abstract: Embodiments of three-dimensional (3D) memory devices having a shielding layer and methods for forming the 3D memory devices are disclosed. In an example, a method for forming a 3D memory device is disclosed. A peripheral device is formed on a first substrate. A first interconnect layer including first interconnect structures are formed above the peripheral device on the first substrate. A shielding layer including a conduction region is formed above the first interconnect layer on the first substrate. The conduction region of the shielding layer covers substantially an area of the first interconnect structures in the first interconnect layer. An alternating conductor/dielectric stack and memory strings each extending vertically through the alternating conductor/dielectric stack are formed on a second substrate. A second interconnect layer including second interconnect structures is formed above the plurality of memory strings on the second substrate.Type: GrantFiled: November 21, 2020Date of Patent: September 12, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Zongliang Huo, Zhiliang Xia, Li Hong Xiao, Jun Chen
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Publication number: 20230254780Abstract: A wireless transmission method includes obtaining an MCS (modulation and coding scheme) rate and a power amplifier gain of each station in a set of stations for a multi-user (MU) transmission, generating a maximum available MCS rate according to a plurality of MCS rates of the set of stations, selecting a power amplifier gain of the MU transmission according to the maximum available MCS rate, adjusting a digital gain of each station according to the power amplifier gain of the MU transmission and the power amplifier gain of each station, adjusting a frequency domain signal of each station according to the digital gain thereof, converting a plurality of adjusted frequency domain signals of the set of stations into a time domain signal, and generating an amplified signal for the MU transmission according to the power amplifier gain of the MU transmission and the time-domain signal.Type: ApplicationFiled: August 22, 2022Publication date: August 10, 2023Applicant: Realtek Semiconductor Corp.Inventors: Zh-Hong Xiao, Shau-Yu Cheng, Wen-Yung Lee, Chun-Kai Tseng, Jhe-Yi Lin
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Patent number: 11706920Abstract: Embodiments of three-dimensional (3D) memory devices having a memory layer that confines electron transportation and methods for forming the same are disclosed. A method for forming a 3D memory device includes the following operations. An initial channel hole is formed in a stack structure having a plurality of first layers and a plurality of second layers alternatingly arranged over a substrate. A portion of each one of the plurality of first layers facing a sidewall of the initial channel hole is removed to form a channel hole. A semiconductor channel structure is formed in the channel hole. The semiconductor channel structure includes a memory layer following a profile of a sidewall of the channel hole. The plurality of first layers are removed to form a plurality of tunnels. Portions of the memory layer are removed, through the tunnels, to divide the memory layer into a plurality of disconnected sub-memory portions.Type: GrantFiled: December 1, 2020Date of Patent: July 18, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Jun Liu, Li Hong Xiao
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Publication number: 20230193566Abstract: The system includes a track lining apparatus and two tamping apparatuses arranged in parallel, wherein the track lining apparatus includes two track lining hydro-cylinders, and the track lining hydro-cylinder communicates with a hydraulic control system through an oil inlet pipeline and an oil return pipeline; pressure sensors configured to detect pressures of the pipelines are provided on the oil inlet pipeline and the oil return pipeline; the tamping apparatus includes two pairs of tamping components arranged on both sides, where the tamping component includes a pair of packer arms and two pairs of packers; a dynamic force sensor is provided at a joint between the packer arm and the packer, and the dynamic force sensor can detect a transient dynamic downward insertion force generated when the packer is inserted into the ballast bed.Type: ApplicationFiled: December 1, 2022Publication date: June 22, 2023Applicant: Beijing Jiaotong UniversityInventors: Liang GAO, Shunwei SHI, Hui YIN, Xiaopei CAI, Meng XU, Hong XIAO, Bowen HOU, Yanglong ZHONG, Yixiong XIAO, Ji WANG
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Patent number: 11665903Abstract: Embodiments of methods to form three-dimensional (3D) memory devices include the following operations. First, an initial channel hole is formed in a stack structure of a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. An offset is formed between a side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers on a sidewall of the initial channel hole to form a channel hole. A semiconductor channel is formed by filling the channel hole with a channel-forming structure, the semiconductor channel having a memory layer including a plurality of first memory portions each surrounding a bottom of a respective second layer and a plurality of second memory portions each connecting adjacent first memory portions.Type: GrantFiled: November 21, 2020Date of Patent: May 30, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventor: Li Hong Xiao
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Publication number: 20230154109Abstract: The present application provides a virtual reality-based derailment accident passenger comfort degree monitoring system and method, wherein the system comprises a train dynamics calculation module, a train operation state virtual simulation module, a six-degree-of-freedom motion platform, a train seat, a head-mounted display, a human body monitoring sensor system and a monitoring data storage terminal. The system establishes a database of the injury degrees of passengers with different ages under the train derailment; the test cost is low, the safety coefficient is high, and the repeatability of the test conditions is good, wherein the comfort degree test data of the passengers under the same derailment inducement can be repeatedly obtained; the safety risk in the actual test is eliminated, so that the authenticity of the test result is ensured, and the test cost is low and the repeatability is high.Type: ApplicationFiled: November 9, 2022Publication date: May 18, 2023Applicant: Beijing Jiaotong UniversityInventors: Liang GAO, Fengzhuang TONG, Jianhua ZHU, Hui YIN, Xiaopei CAI, Tao XIN, Hong XIAO, Yanglong ZHONG, Shuaijie MIAO