Abstract: A wireless transmission method includes obtaining an MCS (modulation and coding scheme) rate and a power amplifier gain of each station in a set of stations for a multi-user (MU) transmission, generating a maximum available MCS rate according to a plurality of MCS rates of the set of stations, selecting a power amplifier gain of the MU transmission according to the maximum available MCS rate, adjusting a digital gain of each station according to the power amplifier gain of the MU transmission and the power amplifier gain of each station, adjusting a frequency domain signal of each station according to the digital gain thereof, converting a plurality of adjusted frequency domain signals of the set of stations into a time domain signal, and generating an amplified signal for the MU transmission according to the power amplifier gain of the MU transmission and the time-domain signal.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.

Abstract: Provided is a touch display substrate. The touch display substrate includes a base substrate, including a display region and a non-display region; a plurality of touch electrodes disposed in the display region; and a plurality of signal transmission circuits, a plurality of first control lines, a plurality of second control lines, a target signal line, and a plurality of touch signal lines that are disposed in the non-display region.

Abstract: A display substrate, a display panel, and a display apparatus. The display substrate includes a base substrate; a gate line extending in a first direction on the base substrate; and a transistor located on the base substrate, where the transistor includes a gate electrode and a first electrode that is located at a side of a layer where the gate electrode is located away from the base substrate, part of the gate line is used as the gate electrode, an orthogonal projection of the gate electrode on the base substrate in a second direction is located within an orthogonal projection of the first electrode on the base substrate in the second direction, and the second direction intersects with the first direction.

Abstract: The present application relates to a 1.5V lithium battery. The lithium battery includes a circuit assembly, a plastic frame, a wound battery core assembly, a first metal housing, a second metal housing, a first insulating seal and an insulating sheath. The wound battery core assembly is arranged in the second metal housing, the first metal housing and the second metal housing dock with each other and fixed by circumferential welding, and the circuit assembly includes a PCB, a low-voltage positive cap, a high-voltage positive connecting piece and a negative elastic piece. In the present application, the circuit assembly can stably output a low voltage of 1.5V.

Abstract: The present application relates to a technical field of separating kavalactone and flavokawain, and in particular, to a method for separating flavokawain and kavalactone, kavalactone, and microencapsulated kavalactone. The separation method includes: S1. grinding root of piper methysticum, extracting by supercritical carbon dioxide and collecting a residue for later use, in which an extraction temperature is 45-50° C. and an extraction pressure is 4-8 MPa; S2. extracting the residue by supercritical carbon dioxide, and collecting extracted oil for later use, in which an extraction temperature is 60-80° C. and an extraction pressure is 20-50 MPa; S3. performing re-extraction and adsorption on the extracted oil to obtain a primary product of the kavalactone; and S4. crystallizing the primary product of kavalactone to obtain the kavalactone. The obtained kavalactone is used for microencapsulated kavalactone.

Abstract: A metro rail corrugation measurement method based the Seq2Seq model and vibration and noise data fusion comprises the following steps: Constructing a time series data set corresponding to floor longitudinal acceleration and train speed based on historical data of metro trains; Constructing the metro train mileage matching prediction model based on the Seq2Seq model, training the metro train mileage matching prediction model by time series data sets, and inputting the inside floor longitudinal acceleration of the metro train to be detected into the trained metro train mileage matching prediction model to obtain the running speed of the metro train to be detected. According to the vibration and noise data of the metro train to be detected, the vibration and noise composite index of the rail corrugation is calculated to determine the wavelength and amplitude information corresponding to the rail corrugation.

Abstract: A method is provided that includes: obtaining current dialogue data; determining a requirement type of the user in the current round of dialogue based on the current dialogue data; in response to the requirement type being an image processing requirement, determining an action sequence for implementing the image processing requirement; executing the action sequence to generate a target image; and generating response data corresponding to the user input data based on the target image.

Abstract: The present application provides a virtual reality-based derailment accident passenger comfort degree monitoring system and method, wherein the system comprises a train dynamics calculation module, a train operation state virtual simulation module, a six-degree-of-freedom motion platform, a train seat, a head-mounted display, a human body monitoring sensor system and a monitoring data storage terminal. The system establishes a database of the injury degrees of passengers with different ages under the train derailment; the test cost is low, the safety coefficient is high, and the repeatability of the test conditions is good, wherein the comfort degree test data of the passengers under the same derailment inducement can be repeatedly obtained; the safety risk in the actual test is eliminated, so that the authenticity of the test result is ensured, and the test cost is low and the repeatability is high.

Abstract: A display panel includes an active area; a fanout region; and a bonding region located on one side, away from the active area, of the fanout region. A driver chip is disposed in the bonding region. The driver chip includes a first side edge adjacent to the fanout region, a second side edge opposite to the first side edge, and two third side edges. The driver chip includes a plurality of output terminals disposed close to the first side edge. The display panel includes: a plurality of fanout lines located in the fanout region; and a plurality of gull-wing lines located in the bonding region. Part of the fanout lines extend from the fanout region to a region where the first side edge is located, and are electrically connected to the output terminals. Another part of the fanout lines are electrically connected to the output terminals via the gull-wing lines.

Abstract: An array substrate is provided. The array substrate includes a plurality of first reset signal lines configured to provide a plurality of first reset signals, a plurality of second reset signal lines configured to provide a plurality of second reset signals, a plurality of third reset signal lines, and a plurality of first connecting lines. A respective first reset signal line is connected to a row of first connecting lines, which in turn are connected to source electrodes of first reset transistors in a row of subpixels, respectively. The plurality of second reset signal lines and the plurality of third reset signal lines form an interconnected reset signal supply network. A respective second reset signal line is connected to one or more of the plurality of third reset signal lines. A respective third reset signal line is connected to one or more of the plurality of second reset signal lines.

Abstract: Provided herein are compounds that can inhibit the replication of influenza viruses, reduce the amount of influenza viruses, and/or treat influenza.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.

Abstract: In an example, a memory device includes a first stack structure and a second stack structure over the first stack structure. Each of the first stack structure and the second stack structure includes alternately stacked conductor layers and first insulating layers. The memory device also includes a first channel structure extending through the first stack structure, and a second channel structure extending through the second stack structure and connected with the first channel structure. A width of an end of the first channel structure closer to the second channel structure is greater than that of the second channel structure closer to the first channel structure. The memory device further includes a pillar structure extending through the first stack structure and the second stack structure. The pillar structure includes a metal layer.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the disclosed method comprises forming a plurality of dielectric stacks stacked on one another over a substrate to create a multiple-stack staircase structure. Each one of the plurality of dielectric stacks comprises a plurality of dielectric pairs arranged along a direction perpendicular to a top surface of the substrate. The method further comprises forming a filling structure that surrounds the multiple-stack staircase structure, forming a semiconductor channel extending through the multiple-staircase structure, wherein the semiconductor channel comprises unaligned sidewall surfaces, and forming a supporting pillar extending through at least one of the multiple-staircase structure and the filling structure, wherein the supporting pillar comprises aligned sidewall surfaces.

Abstract: Embodiments of methods to form three-dimensional (3D) memory devices include the following operations. First, an initial channel hole is formed in a stack structure of a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. An offset is formed between a side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers on a sidewall of the initial channel hole to form a channel hole. A semiconductor channel is formed by filling the channel hole with a channel-forming structure, the semiconductor channel having a memory layer including a plurality of first memory portions each surrounding a bottom of a respective second layer and a plurality of second memory portions each connecting adjacent first memory portions.

Abstract: Embodiments of a channel hole plug structure of 3D memory devices and fabricating methods thereof are disclosed. The memory device includes an alternating layer stack disposed on a substrate, an insulating layer disposed on the alternating dielectric stack, a channel hole extending vertically through the alternating dielectric stack and the insulating layer, a channel structure including a channel layer in the channel hole, and a channel hole plug in the insulating layer and above the channel structure. The channel hole plug is electrically connected with the channel layer. A projection of the channel hole plug in a lateral plane covers a projection of the channel hole in the lateral plane.

Abstract: A 3D-NAND memory device is provided. The memory device includes a substrate, a bottom select gate (BSG) disposed over the substrate, a plurality of word lines positioned over the BSG with a staircase configuration and a plurality of insulating layers disposed between the substrate, the BSG, and the plurality of word lines. In the disclosed memory device, one or more first dielectric trenches are formed in the BSG and extend in a length direction of the substrate to separate the BSG into a plurality of sub-BSGs. In addition, one or more common source regions are formed over the substrate and extend in the length direction of the substrate. The one or more common source regions further extend through the BSG, the plurality of word lines and the plurality of insulating layers.

Abstract: A device area includes at least a first layer of photoresist and a second layer of photoresist. First layer metrology targets are positioned at an edge of one of the sides of the first layer of the mat. The first layer metrology targets have a relaxed pitch less than a device pitch. Secondary electron and back-scattered electron images can be simultaneously obtained.

Abstract: Aspects of the disclosure provide a method for fabricating semiconductor device. The method includes characterizing an etch process that is used to etch channel holes and dummy channel holes in a stack of alternating sacrificial gate layers and insulating layers upon a substrate of a semiconductor device. The channel holes are in a core region and the dummy channel holes are in a staircase region. The stack of alternating sacrificial gate layers and insulating layers extend from the core region into in the staircase region of a stair-step form. The method further includes determining a first shape for defining the dummy channel holes in a layout based on the characterization of the etch process. The first shape is different from a second shape for defining the channel holes.