Abstract: A 3D-NAND memory device is provided. The memory device includes a substrate, a bottom select gate (BSG) disposed over the substrate, a plurality of word lines positioned over the BSG with a staircase configuration and a plurality of insulating layers disposed between the substrate, the BSG, and the plurality of word lines. In the disclosed memory device, one or more first dielectric trenches are formed in the BSG and extend in a length direction of the substrate to separate the BSG into a plurality of sub-BSGs. In addition, one or more common source regions are formed over the substrate and extend in the length direction of the substrate. The one or more common source regions further extend through the BSG, the plurality of word lines and the plurality of insulating layers.

Abstract: An isolated resonant power supply circuit, a magnetic resonance imaging system, and an air-cored transformer is provided. The isolated resonant power supply circuit is disposed within a scan room of a magnetic resonance imaging system. The isolated resonant power supply circuit includes: an inverter circuit, a resonant transformer circuit, and a rectifier circuit. The inverter circuit is connected to the resonant transformer circuit and is used for converting inputted direct current power into alternating current power and outputting the same to the resonant transformer circuit. The resonant transformer circuit is used for performing resonant conversion and transformation on the alternating current power, and then output the same to the rectifier circuit. The rectifier circuit is used for rectifying an alternating current output voltage outputted by the resonant transformer circuit into a direct current voltage for output, so as to supply power.

Abstract: An array base plate and a display apparatus are provided by the present application. The array base plate includes a substrate, an active area and a binding area that are located on the substrate, wherein the binding area is located at one side of the active area; the array base plate further includes: an alignment layer extending from the active area to the binding area; and binding terminals located in the binding area, wherein an orthographic projection of the alignment layer on the substrate does not overlap with orthographic projections of the binding terminals on the substrate; wherein in a direction parallel to a plane where the substrate is located and pointing from the active area to the binding area.

Abstract: A power-supply mode switching circuit and an aerosol generating device are provided. The power-supply mode switching circuit includes an external-power-source power-supply circuit, a protection circuit, and a battery power-supply circuit. A node where the external-power-source power-supply circuit is connected to the protection circuit serves as a power-source input end. A node where the external-power-source power-supply circuit is connected to the battery power-supply circuit serves as a power supply end. The protection circuit is configured to control the battery power-supply circuit to be cut off when the power-source input end is connected to the external power source, to make the external power source supply power to the power supply end. The protection circuit is further configured to control the battery power-supply circuit to be conducted when the power-source input end is not connected to the external power source, to make the battery supply power to the power supply end.

Abstract: The present disclosure provides a gate driving circuit and a display panel. The display panel includes a display area and a peripheral area surrounding the display area. At least one gate driving circuit is arranged in the peripheral area. The at least one gate driving circuit includes a plurality of shift register units cascaded in sequence. The plurality of shift register units include first shift register units and second shift register units. The first shift register units and the second shift register units are spaced apart from each other. The number of transistors in the first shift register units is smaller than the number of transistors in the second shift register units.

Abstract: The present application relates to a voltage-reduced lithium battery and a manufacturing method thereof. The voltage-reduced lithium battery includes a circuit assembly, a plastic frame, a wound battery core assembly, a first metal housing, a second metal housing, an insulating seal and an insulating sheath, wherein the circuit assembly and the plastic frame are arranged in the first metal housing, the wound battery core assembly is arranged in the second metal housing, the first metal housing and the second metal housing are in vertical butt connection and fixed by circumferential welding, the insulating seal is configured to seal the second metal housing, and the insulating sheath covers the first metal housing and the second metal housing.

Abstract: A display panel, a display device and a driving method. The display panel includes a display region and a peripheral region. The display region includes a subpixel unit array having a plurality of rows and a plurality of columns of subpixel units, and the peripheral region includes a gate drive circuit. The display region further includes a plurality of gate lines and a plurality of data lines. The gate drive circuit comprises a plurality of shift register units, and the plurality of gate lines are electrically connected with the plurality of shift register units. The gate drive circuit comprises two shift-register-unit scanning groups, in the shift-register-unit scanning groups, a (k+1)th shift register unit and a (k)th shift register unit form one shift register unit group.

Abstract: Embodiments of 3D memory devices and fabricating methods thereof are disclosed. The method comprises forming an array device semiconductor structure comprising an alternating conductor/dielectric stack disposed on a semiconductor layer, and an array interconnect layer disposed on the alternating conductor/dielectric stack and including a first interconnect structure. The method further comprises a peripheral device disposed on a substrate, and a peripheral interconnect layer disposed on the peripheral device and including a second interconnect structure and a pad. The pad is electrically connected with the peripheral device through the second interconnect structure. The method further comprises bonding the array interconnect layer to the peripheral interconnect layer, such that the first interconnect structure is joined with the second interconnect structure. The method further comprises forming a pad opening exposing a surface of the pad.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.

Abstract: In certain aspects, a method of erasing a memory device is disclosed. The memory device includes a bottom select gate (BSG) and a dielectric trench separating the BSG into a first sub-BSG and a second sub-BSG. A first voltage is applied to the first sub-BSG. A second voltage is applied to the second sub-BSG. The second voltage is different from the first voltage.

Abstract: A wireless transmission method includes obtaining an MCS (modulation and coding scheme) rate and a power amplifier gain of each station in a set of stations for a multi-user (MU) transmission, generating a maximum available MCS rate according to a plurality of MCS rates of the set of stations, selecting a power amplifier gain of the MU transmission according to the maximum available MCS rate, adjusting a digital gain of each station according to the power amplifier gain of the MU transmission and the power amplifier gain of each station, adjusting a frequency domain signal of each station according to the digital gain thereof, converting a plurality of adjusted frequency domain signals of the set of stations into a time domain signal, and generating an amplified signal for the MU transmission according to the power amplifier gain of the MU transmission and the time-domain signal.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.

Abstract: The present application relates to a technical field of separating kavalactone and flavokawain, and in particular, to a method for separating flavokawain and kavalactone, kavalactone, and microencapsulated kavalactone. The separation method includes: S1. grinding root of piper methysticum, extracting by supercritical carbon dioxide and collecting a residue for later use, in which an extraction temperature is 45-50° C. and an extraction pressure is 4-8 MPa; S2. extracting the residue by supercritical carbon dioxide, and collecting extracted oil for later use, in which an extraction temperature is 60-80° C. and an extraction pressure is 20-50 MPa; S3. performing re-extraction and adsorption on the extracted oil to obtain a primary product of the kavalactone; and S4. crystallizing the primary product of kavalactone to obtain the kavalactone. The obtained kavalactone is used for microencapsulated kavalactone.

Abstract: The present application relates to a 1.5V lithium battery. The lithium battery includes a circuit assembly, a plastic frame, a wound battery core assembly, a first metal housing, a second metal housing, a first insulating seal and an insulating sheath. The wound battery core assembly is arranged in the second metal housing, the first metal housing and the second metal housing dock with each other and fixed by circumferential welding, and the circuit assembly includes a PCB, a low-voltage positive cap, a high-voltage positive connecting piece and a negative elastic piece. In the present application, the circuit assembly can stably output a low voltage of 1.5V.

Abstract: A metro rail corrugation measurement method based the Seq2Seq model and vibration and noise data fusion comprises the following steps: Constructing a time series data set corresponding to floor longitudinal acceleration and train speed based on historical data of metro trains; Constructing the metro train mileage matching prediction model based on the Seq2Seq model, training the metro train mileage matching prediction model by time series data sets, and inputting the inside floor longitudinal acceleration of the metro train to be detected into the trained metro train mileage matching prediction model to obtain the running speed of the metro train to be detected. According to the vibration and noise data of the metro train to be detected, the vibration and noise composite index of the rail corrugation is calculated to determine the wavelength and amplitude information corresponding to the rail corrugation.

Abstract: The present application provides a virtual reality-based derailment accident passenger comfort degree monitoring system and method, wherein the system comprises a train dynamics calculation module, a train operation state virtual simulation module, a six-degree-of-freedom motion platform, a train seat, a head-mounted display, a human body monitoring sensor system and a monitoring data storage terminal. The system establishes a database of the injury degrees of passengers with different ages under the train derailment; the test cost is low, the safety coefficient is high, and the repeatability of the test conditions is good, wherein the comfort degree test data of the passengers under the same derailment inducement can be repeatedly obtained; the safety risk in the actual test is eliminated, so that the authenticity of the test result is ensured, and the test cost is low and the repeatability is high.

Abstract: Provided herein are compounds that can inhibit the replication of influenza viruses, reduce the amount of influenza viruses, and/or treat influenza.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.

Abstract: In an example, a memory device includes a first stack structure and a second stack structure over the first stack structure. Each of the first stack structure and the second stack structure includes alternately stacked conductor layers and first insulating layers. The memory device also includes a first channel structure extending through the first stack structure, and a second channel structure extending through the second stack structure and connected with the first channel structure. A width of an end of the first channel structure closer to the second channel structure is greater than that of the second channel structure closer to the first channel structure. The memory device further includes a pillar structure extending through the first stack structure and the second stack structure. The pillar structure includes a metal layer.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the disclosed method comprises forming a plurality of dielectric stacks stacked on one another over a substrate to create a multiple-stack staircase structure. Each one of the plurality of dielectric stacks comprises a plurality of dielectric pairs arranged along a direction perpendicular to a top surface of the substrate. The method further comprises forming a filling structure that surrounds the multiple-stack staircase structure, forming a semiconductor channel extending through the multiple-staircase structure, wherein the semiconductor channel comprises unaligned sidewall surfaces, and forming a supporting pillar extending through at least one of the multiple-staircase structure and the filling structure, wherein the supporting pillar comprises aligned sidewall surfaces.