Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a semiconductor substrate, an alternating layer stack disposed on the semiconductor substrate, and a dielectric structure, which extends vertically through the alternating layer stack, on an isolation region of the substrate. Further, the alternating layer stack abuts a sidewall surface of the dielectric structure and the dielectric structure is formed of a dielectric material. The 3D memory device additionally includes one or more through array contacts that extend vertically through the dielectric structure and the isolation region, and one or more channel structures that extend vertically through the alternating layer stack.

Abstract: Disclosed is a method for forming a staircase structure of 3D memory devices, comprising (i) forming a stack of layers on a substrate; (ii) removing a portion of the stack to form a lower region and a upper region; (iii) forming a mask to cover the lower region and the upper region of the stack; (iv) forming a first opening in the mask to expose a first portion of the stack in the lower region and a second opening in the mask to expose a second portion of the stack in the upper region; (v) forming a photoresist layer to cover the stack and the mask; (vi) using a same set of trim-etch processes to pattern the photoresist layer to form a set of staircases in the first opening and the second opening; (vii) removing the photoresist layer and the mask; and repeating (iii), (iv), (v), (vi) and (vii) sequentially.

Abstract: Embodiments of 3D memory devices and fabricating methods thereof are disclosed. The device comprises an array device semiconductor structure comprising an array interconnect layer disposed on the alternating conductor/dielectric stack and including a first interconnect structure. The device further comprises a peripheral device semiconductor structure comprising a peripheral interconnect layer disposed on a peripheral device and including a second interconnect structure. The device further comprises a pad embedded in the array device semiconductor structure or the peripheral interconnect layer, and a pad opening exposing a surface of the pad. The array interconnect layer is bonded with the peripheral interconnect layer, and the pad is electrically connected with the peripheral device through the first interconnect structure or the second interconnect structure.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the disclosed method comprises forming a plurality of dielectric stacks stacked on one another over a substrate to create a multiple-stack staircase structure. Each one of the plurality of dielectric stacks comprises a plurality of dielectric pairs arranged along a direction perpendicular to a top surface of the substrate. The method further comprises forming a filling structure that surrounds the multiple-stack staircase structure, forming a semiconductor channel extending through the multiple-staircase structure, wherein the semiconductor channel comprises unaligned sidewall surfaces, and forming a supporting pillar extending through at least one of the multiple-staircase structure and the filling structure, wherein the supporting pillar comprises aligned sidewall surfaces.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate having one or more first recesses in a first region and one or more second recesses in a second region. A liner layer is disposed over the sidewalls and bottom of the one or more first recesses in the first region and an epitaxially-grown material is formed in the one or more second recesses in the second region. One or more NAND strings are formed over the epitaxially-grown material disposed in the one or more second recesses, and one or more vertical structures are formed over the one or more first recesses in the first region.

Abstract: A device area includes at least a first layer of photoresist and a second layer of photoresist. First layer metrology targets are positioned at an edge of one of the sides of the first layer of the mat. The first layer metrology targets have a relaxed pitch less than a device pitch. Secondary electron and back-scattered electron images can be simultaneously obtained.

Abstract: Embodiments of three-dimensional (3D) memory devices having a memory layer that confines electron transportation and methods for forming the same are disclosed. A method for forming a 3D memory device includes the following operations. First, an initial channel hole can be formed in a structure. The structure can include a staircase structure. The structure can include a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. An offset can be formed between a side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers on a sidewall of the initial channel hole to form a channel hole. A semiconductor channel can then be formed based on the channel hole. Further, a plurality of gate electrodes can be formed based on the plurality of second layers.

Abstract: Embodiments of 3D memory devices having one or more high-? dielectric layers and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including a high-? dielectric layer above the substrate and a plurality of interleaved conductor and dielectric layers above the high-? dielectric layer, and a semiconductor plug disposed above the substrate and in an opening of the high-? dielectric layer.

Abstract: Embodiments of three-dimensional (3D) memory devices having a memory layer that confines electron transportation and methods for forming the same are disclosed. A method for forming a 3D memory device includes the following operations. An initial channel hole in a structure is formed. The structure includes a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. An offset between a side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers can be formed on a sidewall of the initial channel hole to form a channel hole. The channel hole with a channel-forming structure can be formed to form a semiconductor channel. The channel-forming structure can include a memory layer extending along a vertical direction. The plurality of second layers can then be replaced with a plurality of gate electrodes.

Abstract: A memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first substrate and one or more peripheral devices on the first substrate. The second semiconductor structure includes a first set of conductive lines electrically coupled with a first set of a plurality of vertical structures and a second set of conductive lines electrically coupled with a second set of the plurality of vertical structures different from the first set of the plurality of vertical structures. The first set of conductive lines are vertically distanced from one end of the plurality of vertical structures and the second set of conductive lines are vertically distanced from an opposite end of the plurality of vertical structures.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate and a multiple-stack staircase structure. The multiple-stack staircase structure can include a plurality of staircase structures stacked over the substrate. Each one of the plurality of staircase structures can include a plurality of conductor layers each between two insulating layers. The memory device can also include a filling structure over the multiple-stack staircase structure, a semiconductor channel extending through the multiple-stack staircase structure, and a supporting pillar extending through the multiple-stack staircase structure and the filling structure. The semiconductor channel can include unaligned sidewall surfaces, and the supporting pillar can include aligned sidewall surfaces.

Abstract: Embodiments of staircase and contact structures of a three-dimensional (3D) memory device and fabrication method thereof are disclosed. The 3D memory device includes a semiconductor substrate and a plurality of through-substrate-trenches penetrating the semiconductor substrate. The 3D memory device also includes a film stack disposed on a first surface of the semiconductor substrate extending through the through-substrate-trenches to a second surface of the semiconductor substrate, wherein the film stack includes alternating conductive and dielectric layers. The 3D memory device also includes a staircase structure formed at an edge of the film stack.

Abstract: Methods and systems for managing security in a cloud computing environment are provided. Exemplary methods include: gathering data about workloads and applications in the cloud computing environment; updating a graph database using the data, the graph database representing the workloads of the cloud computing environment as nodes and relationships between the workloads as edges; receiving a security template, the security template logically describing targets in the cloud computing environment to be protected and how to protect the targets; creating a security policy using the security template and information in the graph database; and deploying the security policy in the cloud computing environment.

Abstract: Embodiments of three-dimensional (3D) memory devices with stacked device chips using interposers and fabrication methods thereof are disclosed. In an example, a method for forming a 3D memory device is disclosed. An alternating conductor/dielectric stack is formed at a first side of a chip substrate. A memory string extending vertically through the alternating conductor/dielectric stack is formed. A chip contact is formed at a second side opposite to the first side of the chip substrate and is electrically connected to the memory string. A first interposer contact is formed at a first side of an interposer substrate. A second interposer contact is formed at a second side opposite to the first side of the interposer substrate and is electrically connected to the first interposer contact through the interposer substrate. The first interposer contact is attached to the chip contact.

Abstract: Methods and systems for validating security policy in a cloud computing environment are provided. An example method includes providing a graph database, the graph database representing workloads of the cloud computing environment as nodes and relationships between the workloads as edges, receiving a security policy, the security policy logically describing rules for the relationships between the workloads, determining, based on the security policy and the graph database, a list of violations, the list of violations including at least one relationship from the relationships between the workloads in the graph database, the at least one relationship being not allowed by at least one of the rules in the security policy, and providing the list of violations to a user.

Abstract: Methods and systems for managing security in a cloud computing environment are provided. Exemplary methods include: receiving a target, the target specifying workloads of a plurality of workloads to be included in the security policy, the plurality of workloads being associated with the cloud computing environment; identifying nodes and edges in the graph database using the target, the graph database representing the plurality of workloads as nodes and relationships between the plurality of workloads as edges; getting a security intent, the security intent including a high-level security objective in a natural language; obtaining a security template associated with the security intent; and applying the security template to the identified nodes and edges to produce security rules for the security policy, the security rules at least one of allowing and denying communications between the target and other workloads of the plurality of workloads.

Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. A first device layer is formed above a first substrate. A first bonding layer including a first bonding contact is formed above the first device layer. The first bonding contact is made of a first indiffusible conductive material. A second device layer is formed above a second substrate. A second bonding layer including a second bonding contact is formed above the second device layer. The first substrate and the second substrate are bonded in a face-to-face manner, such that the first bonding contact is in contact with the second bonding contact at a bonding interface.

Abstract: Embodiments of three-dimensional (3D) memory devices having a shielding layer and methods for forming the 3D memory devices are disclosed. In an example, a method for forming a 3D memory device is disclosed. A peripheral device is formed on a substrate. A first interconnect layer including a first plurality of interconnects is formed above the peripheral device. A shielding layer including a conduction region is formed above the first interconnect layer. A second interconnect layer including a second plurality of interconnects is formed above the shielding layer. The conduction region of the shielding layer covers an area of the first and second plurality of interconnects in the first and second interconnect layers. A plurality of memory strings each extending vertically above the second interconnect layer are formed.

Abstract: A scanning type laser induced spectrum surface range analysis and detection system includes a laser emitting head connected to an external laser inducing light source, which generates lasers emitted through the laser emitting head, so as to generate laser induced plasma. A focusing optical device converges induction excited laser beams emitted by the laser emitting head onto a surface of a tested sample. Then, a reflector collects wide spectral range induced plasma scattered light signals of the tested sample and converges the signals into a light collecting device. The light collecting device converges induced plasma scattered light into an optical fiber and transmits the induced plasma scattered light to an external spectrograph; and the external spectrograph divides a spectrum formed by the plasma to obtain spectral strength data of different wavelengths.

Abstract: Embodiments of this application disclose an object on which a two-dimensional code is disposed, a two-dimensional code generation method, identification method, generation apparatus, and identification apparatus, and a storage medium. The two-dimensional code includes a square module array of m*m modules. The square module array includes a location detection pattern and a data information pattern. The location detection pattern is used for determining a location of the two-dimensional code. The data information pattern is used for carrying data. m=17 or 18 or 19 or 20. Even if printed in a miniature area whose side length is 0.5 cm to 0.7 cm, a miniature two-dimensional code provided in the embodiments of this application can still be normally identified, and is suitable for being used in a small area application scenario such as an inner side of a bottle cap or a corner of an object.