Abstract: A method for fabricating an integrated circuit device. A plurality of MOS transistor devices are formed overlying a semiconductor substrate. Each of the MOS transistor devices includes a nitride cap and nitride sidewall spacers. An interlayer dielectric layer is formed overlying the plurality of MOS transistor devices. A portion of the interlayer dielectric material is removed to expose at least portions of three MOS transistor devices and expose at least three regions between respective MOS transistor devices. The method deposits polysilicon fill material overlying the exposed three regions and overlying the three MOS transistor devices. The method performs a chemical mechanical planarization process on the polysilicon material to reduce a thickness of the polysilicon material exposing a portion of the interlayer dielectric material until the cap nitride layer on each of the MOS transistors has been exposed using the cap nitride layer as a polish stop layer.

Abstract: A method for fabricating an integrated circuit device, e.g., DRAM. The method includes providing a semiconductor substrate, e.g., silicon wafer. The method includes forming a plurality of MOS transistor devices overlying the semiconductor substrate. Each of the MOS transistor devices has a nitride cap and nitride sidewall spacers. Each of the transistors is separated from each other by a predetermined width. The method includes forming an interlayer dielectric layer overlying the plurality of MOS transistor devices and removing a portion of the interlayer dielectric material to expose at least portions of three MOS transistor devices and expose at least three regions between respective MOS transistor devices. The method deposits polysilicon fill material overlying the exposed three regions and overlying the three MOS transistor devices.