Patents by Inventor Hong Ye

Hong Ye has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12244116
    Abstract: Apparatus for and method of aligning optical components such as mirrors to facilitate proper beam alignment using an image integration optical system is used to integrate images from multiple optical features such as from both left mirror bank and right mirror bank to present the images simultaneously to the camera system. A fluorescent material may be used to render a beam footprint visible and the relative positions of the footprint and an alignment feature may be used to align the optical feature.
    Type: Grant
    Filed: September 20, 2023
    Date of Patent: March 4, 2025
    Assignee: Cymer, LLC
    Inventor: Hong Ye
  • Publication number: 20250062582
    Abstract: An extended optical pulse stretcher is provided that combines confocal pulse stretchers in combination to produce, for example, 4 reflections, 4 reflections, 12 reflections, and 12 reflections per optical circuit configuration. The inclusion of the combination of different mirror separations and delay path lengths can result in very long pulse stretching, long optical delays, and minimal efficiency losses. Also, in the extended optical pulse stretcher, at least a beam splitter can be positioned relative to the center of curvature of the mirrors to “flatten” each of the circuits to enable the beam to propagate in the same plane (e.g., parallel to the floor). Also, the curvatures and sizes of the individual mirrors can be designed to position the beam splitter closer to one of the banks of mirrors to allow the optical pulse stretchers to properly fit in an allocated location in a laser system.
    Type: Application
    Filed: October 31, 2024
    Publication date: February 20, 2025
    Inventors: Eric Anders Mason, Zhong Quan Zhao, Hong Ye
  • Patent number: 12166327
    Abstract: An extended optical pulse stretcher is provided that combines confocal pulse stretchers in combination to produce, for example, 4 reflections, 4 reflections, 12 reflections, and 12 reflections per optical circuit configuration. The inclusion of the combination of different mirror separations and delay path lengths can result in very long pulse stretching, long optical delays, and minimal efficiency losses. Also, in the extended optical pulse stretcher, at least a beam splitter can be positioned relative to the center of curvature of the mirrors to “flatten” each of the circuits to enable the beam to propagate in the same plane (e.g., parallel to the floor). Also, the curvatures and sizes of the individual mirrors can be designed to position the beam splitter closer to one of the banks of mirrors to allow the optical pulse stretchers to properly fit in an allocated location in a laser system.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: December 10, 2024
    Assignee: Cymer, LLC
    Inventors: Eric Anders Mason, Zhong Quan Zhao, Hong Ye
  • Publication number: 20240379552
    Abstract: Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Yu LO, Chung-Hsing WANG, Chin-Shen LIN, Kuo-Nan YANG, Meng-Xiang LEE, Hao-Tien KAN, Jhih-Hong YE
  • Publication number: 20240353361
    Abstract: A battery pack includes a battery, a first temperature sensor configured to provide a first temperature value associated with a temperature of the battery, a heat source disposed proximate to the battery and configured to heat the battery, a second temperature sensor configured to provide a second temperature value associated with a temperature of the heat source, and a control board coupled to the first temperature sensor and the second temperature sensor, wherein the control board is configured to receive the first temperature value and the second temperature value. The control board is configured to compare the first temperature value and the second temperature value to determine a temperature gradient between the battery and the heat source and transmit an alert if the temperature gradient exceeds a first temperature gradient threshold.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 24, 2024
    Applicant: Google LLC
    Inventors: David Wang, Arun Raghupathy, James Robert Lim, Ihab A. Ali, Chang Hong Ye
  • Publication number: 20240356357
    Abstract: The present document describes techniques for extending battery life after long-term and high-temperature storage. These techniques delay charging of a battery to detect battery conditions and determine whether the battery was exposed to high temperatures while in an idle or low-power state for a long period of time. These techniques include a methodology to relax and refresh an anode surface of the battery, after high-temperature storage, through distinct and tailored discharges prior to beginning a normal charge profile. These techniques can be applied to a wide range of chemistry platforms, which may have kinetic (Li-ion) limitations, to extend the longevity of the battery by reducing lithium plating and capacity degradation caused by long-term, high-temperature storage.
    Type: Application
    Filed: October 26, 2022
    Publication date: October 24, 2024
    Applicant: Google LLC
    Inventors: James Robert Lim, Chang Hong Ye, David Wang, Yuandan Li
  • Publication number: 20240347506
    Abstract: The disclosure provides a method of forming a package structure, and the method includes the following steps. A plurality of semiconductor components is bonded to a substrate. A grinding process is performed to thin the plurality of semiconductor components. The plurality of semiconductor components have a first total thickness variation (TTV) after performing the grinding process. A dielectric layer is formed on the substrate. A first chemical mechanical polishing (CMP) is performed to remove a first portion of the dielectric layer on top surfaces of the plurality of semiconductor components; and performing a second CMP process to remove a second portion of the dielectric layer between the plurality of semiconductor components and a portion of the plurality of semiconductor components. After performing the second CMP process, the plurality of semiconductor components has a second TTV less than the first TTV.
    Type: Application
    Filed: June 26, 2024
    Publication date: October 17, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Hsiu Chen, Ebin Liao, Hong-Ye Shih, Wen-Chih Chiou, Jia-Ling Ko
  • Patent number: 12107048
    Abstract: Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: October 1, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Yu Lo, Chung-Hsing Wang, Chin-Shen Lin, Kuo-Nan Yang, Meng-Xiang Lee, Hao-Tien Kan, Jhih-Hong Ye
  • Publication number: 20240276958
    Abstract: The present disclosure relates to a sgRNA and constructing a dual pig model of severe immunodeficiency and liver injury and use thereof. The method comprises the steps of knocking out RAG2, IL2R? and FAH genes in a porcine fetal fibroblast by using a CRISPR/Cas9 technology, constructing a RAG2?/?/IL2R??/Y/FAH?/? triple-gene edited cloned pig by using a somatic cell nuclear transfer technology, and obtaining a dual pig model of severe immunodeficiency and liver injury through phenotypic analysis and identification. The method overcomes the problems of long production period, low efficiency, irreversible damage, unsatisfactory use in a humanization degree and the like in the existing model construction technology, can realize a batch construction of the dual pig model of severe immunodeficiency and liver injury by a continuous cloning technology, and has great advantages and potential market application prospects in the related fields of tumor biology, cell transplantation, humanized animal models and the like.
    Type: Application
    Filed: April 26, 2024
    Publication date: August 22, 2024
    Inventors: Hong-jiang Wei, Qing-feng Chen, Heng Zhao, De-ling Jiao, Hong-ye Zhao
  • Publication number: 20240258805
    Abstract: The present document describes techniques for safe battery charging during high ambient temperatures. These techniques extend device runtime during peak use periods when ambient temperature is high by increasing the possibility for battery charging during high ambient temperature conditions. In an example, a device, during high ambient temperatures, checks future ambient temperatures over a network to identify if the minimum future ambient temperature over a block of time within the next N number of days is predicted to be sufficiently low that, when combined with device-performance throttling, is estimated to reduce the temperature of the battery to below the maximum charge temperature to enable the battery to be safely charged. The device can also use the future ambient temperatures to budget current battery usage by implementing and/or adjusting device-performance throttling.
    Type: Application
    Filed: December 14, 2022
    Publication date: August 1, 2024
    Applicant: Google LLC
    Inventors: David Wang, Arun Prakash Raghupathy, Chang Hong Ye, Ford Rylander
  • Patent number: 12050190
    Abstract: A battery pack includes a battery, a first temperature sensor configured to provide a first temperature value associated with a temperature of the battery, a heat source disposed proximate to the battery and configured to heat the battery, a second temperature sensor configured to provide a second temperature value associated with a temperature of the heat source, and a control board coupled to the first temperature sensor and the second temperature sensor, wherein the control board is configured to receive the first temperature value and the second temperature value. The control board is configured to compare the first temperature value and the second temperature value to determine a temperature gradient between the battery and the heat source and transmit an alert if the temperature gradient exceeds a first temperature gradient threshold.
    Type: Grant
    Filed: May 4, 2023
    Date of Patent: July 30, 2024
    Assignee: Google LLC
    Inventors: David Wang, Arun Raghupathy, James Robert Lim, Ihab A. Ali, Chang Hong Ye
  • Patent number: 12051672
    Abstract: The disclosure provides a method of forming a package structure, and the method includes: bonding a die to a wafer; performing a thinning process on the die, wherein the die has a first total thickness variation (TTV) after performing the thinning process; forming a dielectric layer on the wafer to cover sidewalls and a top surface the die; performing a first removal process to remove a first portion of the dielectric layer and expose the top surface of the die; and performing a second removal process to remove a second portion of the dielectric layer and a portion of the die, wherein after performing the second removal process, the die has a second TTV less than the first TTV.
    Type: Grant
    Filed: May 31, 2020
    Date of Patent: July 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Hsiu Chen, Ebin Liao, Hong-Ye Shih, Wen-Chih Chiou, Jia-Ling Ko
  • Publication number: 20240030671
    Abstract: Apparatus for and method of aligning optical components such as beam splitters in an optical pulse stretcher in which a landing spot of a beam which has traversed a portion of the optical beam splitter and a coincident landing spot of a beam split from a retroreflected input beam are made to align on a target spot. Also disclosed is an apparatus and method for aligning the retroreflector to facilitate proper beam alignment. A fluorescent material may be used to render a beam landing spot visible.
    Type: Application
    Filed: December 2, 2021
    Publication date: January 25, 2024
    Inventors: Hong Ye, Eric Anders Mason
  • Publication number: 20240014621
    Abstract: Apparatus for and method of aligning optical components such as mirrors to facilitate proper beam alignment using an image integration optical system is used to integrate images from multiple optical features such as from both left mirror bank and right mirror bank to present the images simultaneously to the camera system. A fluorescent material may be used to render a beam footprint visible and the relative positions of the footprint and an alignment feature may be used to align the optical feature.
    Type: Application
    Filed: September 20, 2023
    Publication date: January 11, 2024
    Inventor: Hong Ye
  • Publication number: 20230386976
    Abstract: A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Yung-Chi Lin, Hsin-Yu Chen, Ming-Tsu Chung, HsiaoYun Lo, Hong-Ye Shih, Chia-Yin Chen, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Publication number: 20230373105
    Abstract: A robotic arm capable of picking and placing multi-size wafers includes a first picking and placing unit, a second picking and placing unit and a base. The first picking and placing unit is to transport a first-size or second-size wafer from a first position to a second position. The second picking and placing unit, disposed adjacent to the first picking and placing unit, is to transport the first-size or second-size wafer from the first position to the second position. The base is to construct the first picking and placing unit and the second picking and placing unit. The first picking and placing unit and the second picking and placing unit are identically structured, each of these two units has a frame with adjustable spacing, and thus these two units are able to transport the first-size and second-size wafers simultaneously.
    Type: Application
    Filed: August 23, 2022
    Publication date: November 23, 2023
    Inventors: HUNG-NENG LAI, CHUN-SUNG CHUANG, XIN-HONG YE
  • Patent number: 11823979
    Abstract: A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: November 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Chi Lin, Hsin-Yu Chen, Ming-Tsu Chung, HsiaoYun Lo, Hong-Ye Shih, Chia-Yin Chen, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 11799261
    Abstract: Apparatus for and method of aligning optical components such as mirrors to facilitate proper beam alignment using an image integration optical system is used to integrate images from multiple optical features such as from both left mirror bank and right mirror bank to present the images simultaneously to the camera system. A fluorescent material may be used to render a beam footprint visible and the relative positions of the footprint and an alignment feature may be used to align the optical feature.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: October 24, 2023
    Assignee: Cymer, LLC
    Inventor: Hong Ye
  • Patent number: 11773456
    Abstract: The present disclosure belongs to the technical field of pathogen detection, in particular to loop-mediated isothermal amplification (LAMP) primer sets for detecting porcine susceptibility-related pathogenic bacteria, and a kit, a LAMP chip and use based on the same. The LAMP primer sets for detecting porcine susceptibility-related pathogenic bacteria include an Actinobacillus pleuropneumoniae primer set, a Haemophilus parasuis primer set, a Salmonella choleraesuis primer set, a Bordetella bronchiseptica primer set, a Pasteurella multocida primer set, a Streptococcus suis primer set, and an Erysipelothrix rhusiopathiae primer set.
    Type: Grant
    Filed: August 18, 2022
    Date of Patent: October 3, 2023
    Assignee: Anhui Agricultural University
    Inventors: Xuelan Liu, Yu Li, Jie Tang, Xiaohui Huang, Lin Li, Hong Ye, Yin Dai, Liang Li
  • Publication number: 20230304951
    Abstract: A battery pack includes a battery, a first temperature sensor configured to provide a first temperature value associated with a temperature of the battery, a heat source disposed proximate to the battery and configured to heat the battery, a second temperature sensor configured to provide a second temperature value associated with a temperature of the heat source, and a control board coupled to the first temperature sensor and the second temperature sensor, wherein the control board is configured to receive the first temperature value and the second temperature value. The control board is configured to compare the first temperature value and the second temperature value to determine a temperature gradient between the battery and the heat source and transmit an alert if the temperature gradient exceeds a first temperature gradient threshold.
    Type: Application
    Filed: May 4, 2023
    Publication date: September 28, 2023
    Applicant: Google LLC
    Inventors: David Wang, Arun Raghupathy, James Robert Lim, Ihab A. Ali, Chang Hong Ye