Abstract: An interconnect structure for an integrated circuit, such as a three dimensional integrated circuit (3DIC), and a method of forming the same is provided. An example interconnect structure includes a substrate, a through via extending through the substrate, and a liner disposed between the substrate and the through via. The substrate includes a tapered profile portion. The tapered profile portion abuts the liner.

Abstract: An opposite substrate including a substrate, first light-shielding patterns, second light-shielding patterns, a planarization layer and support members is provided. The support members are located in primary support regions and secondary support regions of the opposite substrate. The first light-shielding patterns respectively extend along a first direction, and a material of the first light-shielding patterns includes an organic material. The second light-shielding patterns respectively extend along a second direction, and a material of the second light-shielding patterns includes metal. The first light-shielding patterns and the second light-shielding patterns are respectively located at opposite sides of the planarization layer. Alternatively, the first light-shielding patterns and the second light-shielding patterns are located at the same side of the planarization layer, and the planarization layer has openings respectively overlapped with the support members located in the secondary support regions.

Abstract: Provided are a method, an apparatus, an electronic device, and a storage medium for displaying an expansion of a 3D shape, including: determining a 3D shape to be expanded, and acquiring a target expanded state of the 3D shape; searching a preset multi-level information relationship table for an articulation relationship set corresponding to the target expanded state; determining, according to the articulation relationship set and a preset expansion rule library, a target expansion rule for each target plane surface on the 3D shape; and controlling to expand each target plane surface at a predetermined a rate based on the each target expansion rule, and displaying the expansion process in real time. The method dynamically displays an expansion process of a 3D shape to a student, such that the student can understands more about the process of transformation from a 3D shape to a selected expanded state, thereby improving user experience of a teaching demonstration function on an electronic device.

Abstract: A backlight module and display device using the same are provided. The backlight module has a light guide plate. A piezoelectric module is arranged at the outer side of the backside surface of the light guide plate and configured to produce a vibration. The vibration is directly or indirectly transmitted to a resonator, for example, a light guide plate or a bezel, to produce resonance, and a space to which the backside surface is oriented is used as a resonance cavity. By means of the arrangement, the screen-to-body ratio of electronic products and the sound quality can be improved while taking into account the thickness and volume of the electronic products.

Abstract: A cushioning device and a packaging assembly for a base station antenna includes an inner cushioning member and an outer cushioning member. Each cushioning member comprises an inflated airbag. The inner cushioning member is configured to abut an end cover of the housing of the base station antenna and to surround at least one protruding member that is provided on the end cover within a cavity defined by the inner cushioning member. The outer cushioning member is configured to cover both ends of the base station antenna.

Abstract: An active device substrate includes a substrate, a first active device, and a second active device. The first active device includes a first gate, a crystallized metal oxide layer, a first insulation layer, a first source, and a first drain. The crystallized metal oxide layer is located on the first gate. The first insulation layer is sandwiched between the crystallized metal oxide layer and the first gate. An area from the top surface of the crystallized metal oxide layer to the bottom surface of the crystallized metal oxide layer is observed via a selected area diffraction mode of a transmission electron microscope, and a diffraction pattern of a crystallized phase can be observed. The second active device includes a second gate, a silicon semiconductor layer, a second source, and a second drain. A manufacturing method of an active device substrate is further provided.

Abstract: A method for skill learning is implemented using a system including a wearable device to be worn by a user, a storage unit, and a processor communicating with the wearable device and the storage unit. The storage unit stores a plurality of virtual reality modules in the storage unit, each of the virtual reality modules containing interactive data associated with learning a skill. The method includes: accessing the storage unit to load a selected one of the virtual reality modules; and controlling the wearable device to present the interactive data contained in the selected one of the virtual reality modules to the user in the form of a virtual environment.

Abstract: An active device substrate includes a substrate, a first active device, and a second active device. The first active device includes a first gate, a crystallized metal oxide layer, a first insulation layer, a first source, and a first drain. The crystallized metal oxide layer is located on the first gate. The first insulation layer is sandwiched between the crystallized metal oxide layer and the first gate. An area from the top surface of the crystallized metal oxide layer to the bottom surface of the crystallized metal oxide layer is observed via a selected area diffraction mode of a transmission electron microscope, and a diffraction pattern of a crystallized phase can be observed. The second active device includes a second gate, a silicon semiconductor layer, a second source, and a second drain. A manufacturing method of an active device substrate is further provided.

Abstract: The present invention relates to a sealing member for a base station antenna and a base station antenna comprising the same as well as a method and device for manufacturing the sealing member. The sealing member (2) is flexible and resilient and is configured to form a seal between an open end (5) of a radome (3) and an end cap (1) of the base station antenna. The sealing member is an elongated sealing strip having two ends, wherein the two ends of the sealing member are lappable with each other, and the sealing member has a groove extending over its entire length, which groove is defined by two side limbs and a bottom limb connecting the two side limbs of the sealing member, wherein the groove is configured to engage with an edge of the open end (5) of the radome, and wherein the sealing member is configured to be received in an annular recess of the end cap (1) and isolate an interior of the radome (3) from the environment.

Abstract: The disclosure provides a method of forming a package structure, and the method includes: bonding a die to a wafer; performing a thinning process on the die, wherein the die has a first total thickness variation (TTV) after performing the thinning process; forming a dielectric layer on the wafer to cover sidewalls and a top surface the die; performing a first removal process to remove a first portion of the dielectric layer and expose the top surface of the die; and performing a second removal process to remove a second portion of the dielectric layer and a portion of the die, wherein after performing the second removal process, the die has a second TTV less than the first TTV.

Abstract: The present application relates to a method for the prevention or treatment of an abnormal cell proliferative disease in a mammal, wherein the method comprises administering to the mammal an effective amount of a 4?-thionucleoside compound or a pharmaceutically acceptable salt, ester, hydrate, solvate thereof, or racemate thereof, or a mixture thereof.

Abstract: The present invention provides two methods for crystallizing a metal oxide semiconductor layer and a semiconductor structure. The first crystallization method is treating an amorphous metal oxide semiconductor layer including indium with oxygen at a pressure of about 550 mtorr to about 5000 mtorr and at a temperature of about 200° C. to about 750° C. The second crystallization method is, firstly, sequentially forming a first amorphous metal oxide semiconductor layer, an aluminum layer, and a second amorphous metal oxide semiconductor layer on a substrate, and, secondly, treating the first amorphous metal oxide semiconductor layer, the aluminum layer, and the second amorphous metal oxide semiconductor layer with an inert gas at a temperature of about 350° C. to about 650° C.

Abstract: Provided is a 3DIC structure includes a wafer, a die and a dielectric layer. The die is over and bonded to the wafer. The dielectric layer is over the wafer and aside the die, covering sidewalls of the die. A total thickness variation (TTV) of the die is less than 0.8 ?m.

Abstract: The present invention relates to a novel compound of 4?-thionucleoside, a preparation method therefor, a pharmaceutical composition comprising the same and an application thereof. Specifically, the present invention relates to a phosphamide derivative of 4?-thionucleoside, a preparation method therefor, a pharmaceutical composition comprising the same, a use thereof in the preparation of a medicine for preventing or treating abnormal cell proliferation diseases (for example, tumors or cancers and related diseases) or virus infectious diseases, and a method of using the same for preventing or treating abnormal cell proliferation diseases (for example, tumors or cancers and related diseases) or virus infectious diseases.

Abstract: An interconnect structure for an integrated circuit, such as a three dimensional integrated circuit (3DIC), and a method of forming the same is provided. An example interconnect structure includes a substrate, a through via extending through the substrate, and a liner disposed between the substrate and the through via. The substrate includes a tapered profile portion. The tapered profile portion abuts the liner.

Abstract: An interconnect structure for an integrated circuit, such as a three dimensional integrated circuit (3DIC), and a method of forming the same is provided. An example interconnect structure includes a substrate, a through via extending through the substrate, and a liner disposed between the substrate and the through via. The substrate includes a tapered profile portion. The tapered profile portion abuts the liner.

Abstract: The present invention provides a method for crystallizing a metal oxide semiconductor layer, a semiconductor structure, a method for manufacturing a semiconductor structure, an active array substrate, and an indium gallium zinc oxide crystal. The crystallization method includes the following steps: forming an amorphous metal oxide semiconductor layer on a substrate; forming an oxide layer on the amorphous metal oxide semiconductor layer; forming an amorphous silicon layer on the oxide layer; and irradiating the amorphous silicon layer by using a laser, so as to heat the amorphous silicon layer, where the heated amorphous silicon layer heats the amorphous metal oxide semiconductor layer, so that the amorphous metal oxide semiconductor layer is converted into a crystallized metal oxide semiconductor layer.

Abstract: The present invention provides two methods for crystallizing a metal oxide semiconductor layer and a semiconductor structure. The first crystallization method is treating an amorphous metal oxide semiconductor layer including indium with oxygen at a pressure of about 550 mtorr to about 5000 mtorr and at a temperature of about 200° C. to about 750° C. The second crystallization method is, firstly, sequentially forming a first amorphous metal oxide semiconductor layer, an aluminum layer, and a second amorphous metal oxide semiconductor layer on a substrate, and, secondly, treating the first amorphous metal oxide semiconductor layer, the aluminum layer, and the second amorphous metal oxide semiconductor layer with an inert gas at a temperature of about 350° C. to about 650° C.

Abstract: A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.

Abstract: A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.