Abstract: The present disclosure describes novel protein kinase inhibitors and methods for preparing them. The pharmaceutical compositions comprising such protein kinase inhibitors and methods of using them for treating cancer and other diseases, conditions, or disorders, which respond to the inhibition of epidermal growth factor receptor (EGFR), anaplastic lymphoma kinase (ALK) activity, or a combination thereof, are also described.

Abstract: A method for performing a motion estimation combined with a Walsh-Hadamard transform algorithm. In image frame, which includes a pixel array to display an image object, the method includes fetching a current image pixel content C and a reference image pixel content R. A Walsh-Hadamard transform algorithm is used to transform the current image pixel content C and the reference image pixel content R, so that a WHT SAD(i, j), WSAD(i,j) is computed to serve as a matching criterion.

Abstract: The invention provides a method for a motion estimation algorithm. The motion estimation algorithm using low bit resolution integrated edge image instead of luminance image to obtain difference block with small AC coefficients, edge image created by filters is employed to improve encoding quality, on the other hand, operation cost is reduced to low bit resolution. The invention also provides a method for a motion estimation algorithm with a new algorithm using low-bit resolution oriented edge image. Using low-bit resolution oriented edge in motion estimation can result in flatter image blocks which is in demanded by texture-compress unit (such as DCT), as a result, the encoding efficiency is improved, and the operation load is reduced by low-bit resolution.

Abstract: A Cyclic Redundancy Check (CRC) system comprises N+1 shift registers. N+1 logic gates having first inputs communicate with outputs of corresponding ones of said N+1 shift registers. N+1 programmable registers store a corresponding CRC coefficient of a 3rd to Nth order CRC polynomial key word, wherein N is an integer greater than two. N+1 multiplexers communicate with outputs of corresponding ones of said N+1 logic gates. At least N of said N+1 multiplexers communicate with corresponding ones of at least N of said N+1 programmable registers.

Abstract: A chaotic circuit for truly random number generation is provided. The chaotic dynamical system used in the circuit is implemented based on the charge redistribution of capacitors. The random number generator circuit is a switched network including four capacitors and eight switches that are controlled by two-phase non-overlapping clock signals. The two clocks turn on switches alternatively. The circuit further includes inverter chain and amplifier. When a first clock signal turns on, four capacitors are charged by the inverter chain and the amplifier that connected as a unity gain buffer. When a second clock signal turns on, the charges are redistributed. The voltage of output terminal of the amplifier is function of its previous status, and thus a random bit stream is generated at an output terminal of the inverter chain. A smaller core area and lower power consumption is provided since circuit is simpler and no resistor is required.

Abstract: A method for performing a motion estimation combined with a Walsh-Hadamard transform algorithm. In image frame, which includes a pixel array to display an image object, the method includes fetching a current image pixel content C and a reference image pixel content R. A Walsh-Hadamard transform algorithm is used to transform the current image pixel content C and the reference image pixel content R, so that a WHT SAD(i, j), WSAD(i,j) is computed to serve as a matching criterion.

Abstract: The invention provides a method for a motion estimation algorithm. The motion estimation algorithm using low bit resolution integrated edge image instead of luminance image to obtain difference block with small AC coefficients, edge image created by filters is employed to improve encoding quality, on the other hand, operation cost is reduced to low bit resolution. The invention also provides a method for a motion estimation algorithm with a new algorithm using low-bit resolution oriented edge image. Using low-bit resolution oriented edge in motion estimation can result in flatter image blocks which is in demanded by texture-compress unit (such as DCT), as a result, the encoding efficiency is improved, and the operation load is reduced by low-bit resolution.

Abstract: An apparatus and a method of fast rotation. A pipeline comprising a plurality of multiplexes a plurality of shifters to perform last rotation of data selected by the multiplexes, and a plurality of adders/subtracters is provided. A plurality sets of data is input to be filtered and selected by the multiplexes. Fast rotation is performed to the data selected by the multiplexes. A final computation is performed a set of resultant data is output through the adder/subtractors.

Abstract: A VLSI wavelet transform (WT) architecture suitable for use in a discrete wavelet transform (DWT) or a discrete wavelet packet transform (DWPT). The WT architecture has a multiplier; an accumulator; at least two address generators that has a first address generator and a second address generator; a control unit; a memory of result that stores computation results; and a memory of table, which pre-stores all possible weights, each of which weights is a product of some specified filter coefficients for performing a DWT/DWPT with parameters of decomposition level, length of data segment, and filter length. The first address generator and the control unit receive data input, the control unit exports control signals to multiplier, accumulator, second address generator, and memory of table.

Abstract: The mobility of mobile subscribers within a wireless digital communications system is estimated based on highway maps and traffic data. Cells within the network are modelled as nodes connected by edges where neighboring cells are connected by roads. Each edge has two edge weight components representing traffic flow from one cell to the other and vice versa. The edge weight components are calculated from terrain factors based on the size or capacity of the roads connecting the two cells and the total traffic within the subject cell, which information may be obtained from commercial geographic databases and/or government agencies. The resulting edge weight represents an expected number of handoffs between the two cells. The problem of partitioning cells among available switches within the network is thus reduced to the purely mathematical problem of minimizing the total edge weights of edges intersected by the partition boundaries.

Abstract: A method and an apparatus for controlling calculation error produced by the accumulation error due to digit truncation in a non-integer computation. The error is eliminated by controlling the values of LSB, C.sub.in and the addition/subtraction selecting signal as, so that C.sub.in is not necessarily equal to C.sub.in. Considering a even number of cascaded pipelines, C.sub.in in the odd pipelines is set as 0, wherein C.sub.in in the even pipelines is set as 1. The resultant error is thus eliminated mutually by odd and even pipelines.

Abstract: A method of signal compression. An input signal is divided into a plurality of segments. Each of the segments is decomposed by wavelet packet transform to a plurality of levels, so that each of the segments is in a form of a group of coefficients in each of a plurality of domains corresponding to each of the levels. Each of the domains is divided into a plurality of sub-domains to calculate a degree of characteristic concentration corresponding thereto. One of the domains having a highest degree of characteristic concentration is select to perform bit allocation and quantization, so that the group of coefficients in the selected domain is represented as an information. The information is formatted into a frame for transmission, and then the frame is output.

Abstract: A systolic linear-array modular multiplier is provided, which can perform the modular multiplication algorithm of P. L. Montgomery more efficiently. The total execution time for n-bit modular multiplication is 2n+11 cycles. The modular multiplier includes a linear array of processing elements which is constructed based on a pipeline architecture that can reduce the computation procedure by one clock period. Each of the processing elements is simple in structure, which is composed of four full adders and fourteen flip-flops. For n-bit modular multiplication, a total number of 46n+184 gates is required, which is substantially less as compared to the prior art, so that manufacturing cost of the modular multiplier can be significantly reduced. These features make the modular multiplier suitable for use in VLSI implementation of modular exponentiation which is the kernel computation in many public-key cryptosystems, such as the RSA (Rivest-Shamir-Adleman) system. With the 0.8 .mu.

Abstract: A current-mode four-quadrant analog multiplier is provided, which is constructed based on CMOS (complementary metal-oxide semiconductor) technology, capable of generating an output current signal which is proportional in magnitude to the product of two input current signals. This current-mode analog multiplier is designed based on the translinear circuit principle. The current-mode analog multiplier has high precision, wide current dynamic range, and is insensitive to temperature and process, suitable for use in VLSI implementation of many analog circuits and systems, such as fuzzy logic controllers and analog neural networks.

Abstract: An adaptive block-matching motion estimator for used in a video coding system wherein the adaptive block-matching motion estimator is less in hardware complexity and latency time and is therefore more cost-effective to implement and higher in performance.

Abstract: A process for obtaining a motion vector for motion estimation used in a video image analysis, utilizing a block matching algorithm, which has the effect of reducing the computational load that is placed on the hardware logic used for implementation of the process. In a process of obtaining the absolute error value for the compared image block, a preliminary comparison is performed for every processed pixel in the image block to determine if the set minimum value of the absolute error function represented by a motionless tolerance constant is achieved. It is not necessary to obtain every actual value of the absolute error function. The block matching scheme of providing motion estimation enables hardware implementing the process to discontinue processing if the desired motion vector is selected prior to all image blocks being compared.

Abstract: An apparatus for implementing motion estimation block matching for video image processing. The apparatus receives pixel data of original and compared image blocks for comparison, to obtain an image motion vector. The apparatus has a multi-stage pipelined tree-architecture that includes a computation stage, a summation section, an accumulation stage, and a minimum value evaluation stage. The computation stage includes 2.sup.n computation members for producing a difference error value and a sign bit of the compared image blocks. The summation section coupled at the pipelined stage next to the computation stage, includes a series of summation stages for producing an absolute error value of the compared image blocks. A following accumulation stage adds an output of the single adder means of the last summation stage and a last un-added sign bit, for producing a sum.