Abstract: An image processing method and an image processing apparatus are provided. The image processing method includes obtaining a panoramic image to which a room corresponds; performing door detection on the panoramic image to determine first information related to at least one door in the room; and displaying, based on the first information, a panoramic identifier of the at least one door in the panoramic image, the panoramic identifier indicating at least a door outline, a door type and an opening type of the door.

Abstract: Provided are a display panel and a display device. The display panel includes: a base substrate, including a display region and a peripheral region, the peripheral region being located on at least one side of the display region; a plurality of sub-pixels, located in the display region; a plurality of constant voltage lines, arranged in a first direction, each of the plurality of constant voltage lines extending in a second direction, the constant voltage line being at least partially located in the display region, and the first direction intersecting with the second direction; and a conductive line, located in the peripheral region, and connected with the plurality of constant voltage lines, the plurality of constant voltage lines being configured to provide a constant voltage to the plurality of sub-pixels.

Abstract: A rail mounting assembly for supporting a pair of electrical components on a case of a server is disclosed. The assembly includes a first mounting structure for receiving a first electrical component; a second mounting structure for receiving a second electrical component; and a single rail fixed between the first mounting structure and the second mounting structure, the single rail having an I-shaped cross-section. The single rail includes a first groove configured to engage with the first electrical component when the first electrical component is mounted to the first mounting structure, and a second groove configured to engage with the second electrical component when the second electrical component is mounted to the second mounting structure. A distance between the first electrical component engaged with the first groove and the second electrical component engaged with the second groove is less than 5 mm, preferably equal to or less than 4 mm.

Abstract: A method and an apparatus for determining a connection relation of subspaces, and a non-transitory computer-readable recording medium are provided. In the method, a plurality of sets of panoramic images respectively corresponding to two respective adjacent subspaces are obtained. Each set of the panoramic images includes two first panoramic images, and a second panoramic image photographed at a connection opening. Orientations of the connection openings are determined based on positions of the connection openings, and orientations of a camera. Relative positions of the two adjacent subspaces are determined based on correspondence relations between the two first panoramic images and parts of the respective second panoramic images. The connection relation of the subspaces is determined based on the connection relation determined based on the same subspace, the orientations of the connection openings, and the relative positions of the two adjacent subspaces.

Abstract: An array substrate is provided. The array substrate includes a plurality of first reset signal lines configured to provide a plurality of first reset signals, a plurality of second reset signal lines configured to provide a plurality of second reset signals, a plurality of third reset signal lines, and a plurality of first connecting lines. A respective first reset signal line is connected to a row of first connecting lines, which in turn are connected to source electrodes of first reset transistors in a row of subpixels, respectively. The plurality of second reset signal lines and the plurality of third reset signal lines form an interconnected reset signal supply network. A respective second reset signal line is connected to one or more of the plurality of third reset signal lines. A respective third reset signal line is connected to one or more of the plurality of second reset signal lines.

Abstract: A display substrate includes: a base substrate and a plurality of sub-pixels arranged on the base substrate, the sub-pixel include a sub-pixel driving circuit, the sub-pixel driving circuit includes: a first transistor, a driving transistor, and a first conductive connection portion; a first electrode of the first transistor is coupled to a second electrode of the driving transistor, a second electrode of the first transistor and a first end portion of the first conductive connection portion are arranged at different layers, the second electrode of the first transistor and the first end portion of the first conductive connection portion are coupled through a via hole; a second end portion of the first conductive connection portion is coupled to a gate electrode of the driving transistor.

Abstract: An electronic cigarette is provided. The electronic cigarette includes a main body and a cigarette cartridge. The main body includes an accommodating slot and a magnetic valve. The magnetic valve movably protrudes from a bottom surface of the accommodating slot. The cigarette cartridge includes a joint surface and a magnetic body that is disposed on the joint surface. The cigarette cartridge is configured to be disposed in the accommodating slot. The magnetic body attracts the magnetic valve to move and protrude from the bottom surface of the accommodating slot, so that the magnetic body is connected to the magnetic valve, and an interval is formed between the cigarette cartridge and the main body.

Abstract: Disclosed is an image processing method including steps of obtaining a plurality of sets of training data, each set of training data containing data of first and second images, image quality of the second image being higher than that of the first image, shooting contents of the first image being the same model, letting the data of the first image be an input of the model, and utilizing the plurality of sets of training data to train the model until a difference feature value between an output of the model and the data of the second image is minimum; and inputting data of a third image to be processed into the model so as to output data of a fourth image after image enhancement, image quality of the fourth image being higher than that of the third image.

Abstract: An array substrate is provided, comprising a plurality of signal lines; wherein a respective signal line of the plurality of signal lines comprises a first portion in a first area and a second portion in a second area, the first portion and the second portion being in different layers; second portions of the plurality of signal lines are grouped into a plurality of pairs, a respective pair comprising a first-second portion and a second-second portion of two adjacent signal lines of the plurality of signal lines; and an orthographic projection of the first-second portion on a base substrate and an orthographic projection of the second-second portion on the base substrate at least partially overlap with each other.

Abstract: Signal lines in the pin field of a printed circuit board layout are modified to reduce line impedance and improve signal integrity. The widths of signal lines are extended in the pin field to take full advantage of the available routing space between pads and adjacent signal lines. The signal line extension can be considered a subtractive approach in that the signal lines are extended to occupy the available muting space, with signal line extensions that would otherwise cause design rule violations being subtracted out. The edge of a signal line is extended to a keep-out region associated with a centerline that extends through a plurality of pads arranged in a line and located adjacent to the signal line. The edge of the signal line is also extended to keep-out regions associated with pads in the pin fields.

Abstract: Display substrate, manufacturing method thereof and display apparatus are provided. The display substrate includes display and periphery areas, and further includes: first and second signal lines, first and second planarization layers, where each of first and second signal lines is located at periphery area, and includes portion extending in first direction; at least part of first signal line is located between display area and second signal line, first spacing region is provided between projection of first signal line onto base of display substrate and projection of second signal line onto base; first planarization portion including first planarization portion located at periphery area; second planarization layer including first via hole, projection of which onto base overlaps with first spacing region at first overlap region; and projection of first planarization portion onto base overlaps with first overlap region at second overlap region.

Abstract: The present invention relates to a foamable composition used to prepare foamed thermoplastic polyurethane and a microwave molded body thereof. The foamable composition includes unfoamed thermoplastic polyurethane particles, a thickener or a bridging agent, and a foaming agent, wherein the unfoamed thermoplastic polyurethane particles have a viscosity of 1,000 poise to 9,000 poise measured at 170° C. according to JISK 7311 test method.

Abstract: Disclosed is a display substrate, comprising a base, and a semiconductor layer, a fourth conductive layer, a second flat layer, and an anode layer sequentially provided on the base. The fourth conductive layer comprises a first anode connection electrode and a second anode connection electrode. The second flat layer comprises a first opening and a second opening. The anode layer comprises a first anode and a second anode. The first anode connection electrode is connected to the first anode through the first opening. The second anode connection electrode is connected to the second anode through the second opening. The area of an orthographic projection of the first anode connection electrode on the base is greater than that of the second anode connection electrode on the base. The area of an orthographic projection of the first opening on the base is greater than that of the second opening on the base.

Abstract: Provided are a passivation layer for forming a semiconductor bonding structure, a sputtering target making the same, a semiconductor bonding structure and a semiconductor bonding process. The passivation layer is formed on a bonding substrate by sputtering the sputtering target; the passivation layer and the sputtering target comprise a first metal, a second metal or a combination thereof. The bonding substrate comprises a third metal. Based on a total atom number of the surface of the passivation layer, O content of the surface of the passivation layer is less than 30 at %; the third metal content of the surface of the passivation layer is less than or equal to 10 at %. The passivation layer has a polycrystalline structure. The semiconductor bonding structure sequentially comprises a first bonding substrate, a bonding layer and a second bonding substrate: the bonding layer is mainly formed by the passivation layer and the third metal.

Abstract: A mounting system is disclosed that includes a bracket configured to mount an object on a structure. The bracket includes a front panel, two side panels extending from the front panel, and a plurality of slots. Each slot is configured to accept a projection connected to the object and retain the projection within the slot. The bracket further includes a plurality of apertures. The mounting system further includes a retainer configured to extend into the bracket through the plurality of apertures and prevent, at least in part, the plurality of projections, retained by the bracket in the plurality of slots, from being withdrawn from the plurality of slots.

Abstract: One aspect provides a power sourcing equipment controller for providing power to a powered device using power-over-Ethernet (PoE). The power sourcing equipment includes a voltage-output logic block to output a sequence of voltage signals, the voltage signals comprising at least a detection signal and a classification signal; a current-measurement logic block to measure current provided responsive to the voltage signals; a backoff-time-determination logic block to determine a backoff time in response to the current-measurement logic block detecting the provided current exceeding a predetermined threshold, the backoff time being determined based on an amount of time needed for discharging an internal capacitor associated with the powered device; and a timing logic block to cause the voltage-output logic block to delay the output of a next sequence of voltage signals based on the determined backoff time, thereby facilitating powering up of a device compliant with a different PoE standard.

Abstract: Disclosed are an image matching method and apparatus. The image matching method is inclusive of steps of obtaining a panoramic image of at least one subspace in a 3D space and a 2D image of the 3D space; acquiring a 2D image of the at least one subspace in the 3D space; performing 3D reconstruction on the panoramic image of the at least one subspace, and procuring a projection image corresponding to the panoramic image of the at least one subspace; and attaining a matching relationship between the panoramic image of the at least one subspace and the 2D image of the at least one subspace, and establishing an association relationship between the panoramic image of the at least one subspace and the 2D image of the at least one subspace between which the matching relationship has been generated.

Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate, at least one group of contact pads, a plurality of first light-emitting elements, a plurality of first pixel driving circuits, a plurality of connecting traces, a plurality of data lines and a plurality of leads. The display area includes a first display area and a second display area; the first light-emitting elements are located in the first display area; the first pixel driving circuits are located in the second display area; the leads are located in the first display area and the peripheral area, and connect the data lines and the at least one group of contact pads; orthographic projections of the first light-emitting elements on a substrate surface of the base substrate are at least partly overlapped with orthographic projections of the leads on the substrate surface of the base substrate.

Abstract: A display substrate, a preparation method thereof, and a display device are provided. The display substrate includes: a substrate, and a drive structure layer and a light-emitting structure layer that are sequentially stacked on the substrate and located in a display region. The display substrate further includes: M rows of scanning signal lines and M rows of light-emitting signal lines. The light-emitting structure layer includes: M rows and N columns of light-emitting structures. The drive structure layer includes: a pixel circuit array and a drive circuit array that extend in a column direction. The pixel circuit array and the drive circuit array are sequentially arranged in a row direction. The pixel circuit array includes: M rows and N columns of pixel circuits, and the pixel circuits are in one-to-one correspondence with the light-emitting structures and electrically connected to corresponding light-emitting structures.

Abstract: A display substrate includes a display region and a non-display region surrounding the display region. The display substrate further includes: a plurality of scanning lines, a plurality of data lines, and a plurality of data fanout lines, at least a part of each data fanout line being located at the non-display region. Each data fanout line is coupled to a corresponding data line, the plurality of data fanout lines includes a plurality of first data fanout lines and a plurality of second data fanout lines, the first data fanout lines are arranged at a same layer, and made of a same material, as the scanning lines, and the second data fanout lines are arranged at a same layer, and made of a same material, as the data lines.