Abstract: The present disclosure provides a calibration method and readable computer storage medium. The calibration method includes: configuring a reference signal source to output a reference signal; delaying the reference signal through a delay chain to output a delay signal; synchronous sampling the reference signal and the delay signal; adding 1 count and obtaining a final count value when the sampling result is in the preset state; determining whether a ratio between the count value and the first quantity is within a preset range; obtaining the average delay time according to the time width of the reference signal wave and the number of the delay units opened in the delay chain when the ratio is within the preset range; and outputting a control signal to the clock recovery circuit according to the average delay time to calibrate the delay time of the clock recovery circuit.

Abstract: The present disclosure provides a calibration method and readable computer storage medium. The calibration method includes: configuring a reference signal source to output a reference signal; delaying the reference signal through a delay chain to output a delay signal; synchronous sampling the reference signal and the delay signal; adding 1 count and obtaining a final count value when the sampling result is in the preset state; determining whether a ratio between the count value and the first quantity is within a preset range; obtaining the average delay time according to the time width of the reference signal wave and the number of the delay units opened in the delay chain when the ratio is within the preset range; and outputting a control signal to the clock recovery circuit according to the average delay time to calibrate the delay time of the clock recovery circuit.

Abstract: A sample holding circuit includes a signal input terminal, a first sampling unit, a second sampling unit, and a holding unit. The signal input terminal receives a first reference voltage or a second reference voltage, the first sampling unit samples the first reference voltage when a first clock signal is triggered to obtain a first sampling voltage, the second sampling unit samples the second reference voltage when a second clock signal is triggered to obtain a second sampling voltage. The holding unit receives the first sampling voltage and the second sampling voltage when a third clock signal is triggered. The sample holding circuit effectively simplifies circuit structure and reduces the use of amplifiers, also improving the signal to noise ratio.

Abstract: A sample holding circuit includes a signal input terminal, a first sampling unit, a second sampling unit, and a holding unit. The signal input terminal receives a first reference voltage or a second reference voltage, the first sampling unit samples the first reference voltage when a first clock signal is triggered to obtain a first sampling voltage, the second sampling unit samples the second reference voltage when a second clock signal is triggered to obtain a second sampling voltage. The holding unit receives the first sampling voltage and the second sampling voltage when a third clock signal is triggered. The sample holding circuit effectively simplifies circuit structure and reduces the use of amplifiers, also improving the signal to noise ratio.

Abstract: A driving method comprising: acquiring a first grayscale value of each of the plurality of pixels in a current display frame; acquiring an area identifier of each of the plurality of pixels and a light-intensity of a surrounding environment, the plurality of pixels comprising at least two kinds of area identifiers, each of the plurality of pixels having a light reflectivity, the area identifier of each of the plurality of pixels being set according to the light reflectivity; converting the first grayscale value of each of the plurality of pixels into a second grayscale value according to the area identifier and the light-intensity of the surrounding environment; and driving the display device to display images according to the second grayscale value of each of the plurality of pixels. The driver and the display device are also provided.

Abstract: A time controller is able to convert and present the LCD display of gray levels within images with a brightness equal to that within the original images. The time controller alternates in operation between first and second modes of gamma correction, each for a specified time duration. In the first correction mode, the time controller corrects the original gray levels in a correction-positive manner and outputs first correction gray levels. In the second correction mode, the time controller corrects the original gray levels in a correction-negative manner, and outputs the second correction gray levels. The first correction gray level is equal to or larger than the second correction gray level, to correspond with original gray levels.

Abstract: A time controller is able to convert and present the LCD display of gray levels within images with a brightness equal to that within the original images. The time controller alternates in operation between first and second modes of gamma correction, each for a specified time duration. In the first correction mode, the time controller corrects the original gray levels in a correction-positive manner and outputs first correction gray levels. In the second correction mode, the time controller corrects the original gray levels in a correction-negative manner, and outputs the second correction gray levels. The first correction gray level is equal to or larger than the second correction gray level, to correspond with original gray levels.

Abstract: A driving control circuit with a compensating circuit detects pixel driving circuits in a display apparatus for compensating a threshold voltage in the pixel driving circuits. The compensating circuit electrically connects with the pixel driving circuits through a corresponding monitoring line. The pixel driving circuit sequentially operates during a detecting time period and a displaying period. Each pixel driving circuit comprises a driving transistor and an OLED. During the detecting time period, the compensating circuit charges a node in each pixel driving circuit by a constant current for speeding up a time of the detecting time period. The node is connected between a terminal of the driving transistor and the OLED in each pixel driving circuit.

Abstract: A driving control system for driving pixel driving circuits in a display apparatus includes a selecting module, a compensating circuit, and a controller. The pixel driving circuit sequentially operates during a detecting time period and a displaying period. Each pixel driving circuit comprises a driving transistor and an OLED. During the detecting time period, the selecting circuit selects at least one of the pixel driving circuits, the driving transistor in the selected at least one of the pixel driving circuits becomes saturated, the compensating circuit detects a detecting current of the selected pixel driving circuit and converts the detecting current into a specified parameter, the controller adjusts a driving voltage provided to the selected pixel driving circuit based on the specified parameter.

Abstract: A driving control system for driving pixel driving circuits in a display apparatus includes a selecting module, a compensating circuit, and a controller. The pixel driving circuit sequentially operates during a detecting time period and a displaying period. Each pixel driving circuit comprises a driving transistor and an OLED. During the detecting time period, the selecting circuit selects at least one of the pixel driving circuits, the driving transistor in the selected at least one of the pixel driving circuits becomes saturated, the compensating circuit detects a detecting current of the selected pixel driving circuit and converts the detecting current into a specified parameter, the controller adjusts a driving voltage provided to the selected pixel driving circuit based on the specified parameter.

Abstract: A driving control circuit with a compensating circuit detects pixel driving circuits in a display apparatus for compensating a threshold voltage in the pixel driving circuits. The compensating circuit electrically connects with the pixel driving circuits through a corresponding monitoring line. The pixel driving circuit sequentially operates during a detecting time period and a displaying period. Each pixel driving circuit comprises a driving transistor and an OLED. During the detecting time period, the compensating circuit charges a node in each pixel driving circuit by a constant current for speeding up a time of the detecting time period. The node is connected between a terminal of the driving transistor and the OLED in each pixel driving circuit.