Patents by Inventor Hong ZHONGSHAN

Hong ZHONGSHAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11164949
    Abstract: A semiconductor structure and a formation method thereof are provided. The formation method includes: providing a substrate and a fin, a gate structure being formed on the substrate, the gate structure spanning the fin and covering a partial sidewall and a partial top of the fin, and a source/drain doping region being formed in the fin on both sides of the gate structure; forming a first dielectric layer on the substrate, the first dielectric layer exposing the top of the fin; forming an etch stop layer to conformally cover the first dielectric layer and the fin and the source/drain doping region exposed by the first dielectric layer; forming a second dielectric layer on the etch stop layer; and forming a conductive plug penetrating through the second dielectric layer and the etch stop layer, the conductive plug spanning the fin, and the conductive plug being connected to the source/drain doping region.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: November 2, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Wang Yan, Fu Xiao, Hong Zhongshan
  • Publication number: 20200411652
    Abstract: A semiconductor structure and a formation method thereof are provided. The formation method includes: providing a substrate and a fin, a gate structure being formed on the substrate, the gate structure spanning the fin and covering a partial sidewall and a partial top of the fin, and a source/drain doping region being formed in the fin on both sides of the gate structure; forming a first dielectric layer on the substrate, the first dielectric layer exposing the top of the fin; forming an etch stop layer to conformally cover the first dielectric layer and the fin and the source/drain doping region exposed by the first dielectric layer; forming a second dielectric layer on the etch stop layer; and forming a conductive plug penetrating through the second dielectric layer and the etch stop layer, the conductive plug spanning the fin, and the conductive plug being connected to the source/drain doping region.
    Type: Application
    Filed: March 13, 2020
    Publication date: December 31, 2020
    Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Wang YAN, Fu XIAO, Hong ZHONGSHAN