Abstract: A method of fabricating a thin-film transistor (TFT) array substrate including forming a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming a semiconductor layer on the gate insulating layer, forming an ohmic contact layer on the semiconductor layer, and forming a source electrode and a drain electrode comprising a plurality of metal layer patterns on the ohmic contact layer, in which the semiconductor layer, the ohmic contact layer, the source electrode and the drain electrode are formed through a single mask process, and one of the plurality of metal layer patterns is etched through a polishing process to form the source electrode and the drain electrode.

Abstract: A method of fabricating a thin-film transistor (TFT) array substrate including forming a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming a semiconductor layer on the gate insulating layer, forming an ohmic contact layer on the semiconductor layer, and forming a source electrode and a drain electrode comprising a plurality of metal layer patterns on the ohmic contact layer, in which the semiconductor layer, the ohmic contact layer, the source electrode and the drain electrode are formed through a single mask process, and one of the plurality of metal layer patterns is etched through a polishing process to form the source electrode and the drain electrode.

Abstract: A display substrate includes a gate metal pattern including a gate line extending in a first direction, a gate electrode electrically connected to the gate line and a storage line, a data metal pattern including a data line extending in a second direction crossing the first direction, a source electrode electrically connected to the data line and a drain electrode spaced apart from the source electrode, a repair electrode extending in the second direction and overlapping the storage line, an organic layer disposed on the data metal pattern and a pixel electrode disposed on the organic layer and electrically connected to the drain electrode.

Abstract: Disclosed herein is a backlight unit, the backlight unit comprises a light guide plate; a wavelength conversion layer disposed above the light guide plate; and a reflective polarizing layer disposed above the wavelength conversion layer and comprising a patterned polarizer, wherein the wavelength conversion layer and the reflective polarizing layer are integrally formed as one piece.

Abstract: A display substrate includes a gate metal pattern including a gate line extending in a first direction, a gate electrode electrically connected to the gate line and a storage line, a data metal pattern including a data line extending in a second direction crossing the first direction, a source electrode electrically connected to the data line and a drain electrode spaced apart from the source electrode, a repair electrode extending in the second direction and overlapping the storage line, an organic layer disposed on the data metal pattern and a pixel electrode disposed on the organic layer and electrically connected to the drain electrode.

Abstract: A display substrate includes a gate metal pattern including a gate line extending in a first direction, a gate electrode electrically connected to the gate line and a storage line, a data metal pattern including a data line extending in a second direction crossing the first direction, a source electrode electrically connected to the data line and a drain electrode spaced apart from the source electrode, a repair electrode extending in the second direction and overlapping the storage line, an organic layer disposed on the data metal pattern and a pixel electrode disposed on the organic layer and electrically connected to the drain electrode.

Abstract: A liquid crystal display including a display panel having data link lines, data lines, scan lines, and pixels connected to the data lines and the scan lines, a source drive integrated circuit configured to supply data voltages to the data lines via the data link lines, and a scan driver configured to provide scan signals to the scan lines. A p-th (p is a positive integer) data link line is connected to a (p+1)-th data line, and a (p+1)-th data link line is connected to a p-th data line.

Abstract: A display substrate includes a first gate line configured to receive a first gate clock, a second gate line adjacent to the first gate line and configured to receive a second gate clock, a first data line configured to transfer a first data signal inverted according to the first gate clock and the second gate clock, where the first data signal has a first polarity, a second data line configured to transfer a second data signal inverted according to the first gate clock and the second gate clock, where the second data signal has a second polarity different from the first polarity, a first pixel including a first high sub pixel electrically connected to the first gate line and the first data line, and a first low sub pixel electrically connected to the first gate line and the second data line.

Abstract: A display substrate includes a gate metal pattern comprising a gate line extending in a first direction and a gate electrode electrically connected to the gate line, a data metal pattern comprising a data line extending in a second direction crossing the first direction, a source electrode electrically connected to the data line and a drain electrode spaced apart from the source electrode, an organic layer disposed on the data metal pattern, a repair hole penetrating the organic layer and exposing a crossing area in which the gate line crosses with the data line and a pixel electrode disposed on the organic layer and electrically connected to the drain electrode.

Abstract: A display substrate includes a first switching element, an organic layer disposed on the first switching element, a capping layer disposed on the organic layer and a cover electrode covering the first emission hole. The first switching element is electrically connected to a gate line extending in a first direction, a data line extending in a second direction crossing the first direction and the pixel electrode disposed adjacent to the data line. The capping layer includes a first emission hole. The cover electrode overlaps the gate line as a first width. The cover electrode overlaps the first switching element as a second width. The second width is smaller than the first width.

Abstract: A display substrate includes a gate metal pattern including a gate line extending in a first direction, a gate electrode electrically connected to the gate line and a storage line, a data metal pattern including a data line extending in a second direction crossing the first direction, a source electrode electrically connected to the data line and a drain electrode spaced apart from the source electrode, a repair electrode extending in the second direction and overlapping the storage line, an organic layer disposed on the data metal pattern and a pixel electrode disposed on the organic layer and electrically connected to the drain electrode.

Abstract: In a method of forming an alignment layer, a first substrate, a second substrate opposite to the first substrate and a liquid crystal layer including a reactive mesogen are formed on a stage on which a groove is formed. The liquid crystal layer is disposed between the first and second substrates. An alignment layer is formed by exposing the liquid crystal layer to harden the reactive mesogen. Although the first and second substrates have a curved shape, the pretilt angles of the first and second alignment layers are matched such that a transmittance of the display panel increases and a response time decreases.

Abstract: A thin film transistor array panel includes: first to third gate lines extending in one direction and parallel to each other; a data line insulated from and intersecting the first to third gate lines; a first thin film transistor connected to the first gate line and the data line; a second thin film transistor connected to the second gate line and an output terminal of the first thin film transistor; a third thin film transistor connected to the third gate line and the data line; a fourth thin film transistor connected to the second gate line and an output terminal of the third thin film transistor; and first to fourth sub-pixel electrodes respectively connected to the first to fourth thin film transistors.

Abstract: A display substrate includes a gate metal pattern comprising a gate line extending in a first direction and a gate electrode electrically connected to the gate line, a data metal pattern comprising a data line extending in a second direction crossing the first direction, a source electrode electrically connected to the data line and a drain electrode spaced apart from the source electrode, an organic layer disposed on the data metal pattern, a repair hole penetrating the organic layer and exposing a crossing area in which the gate line crosses with the data line and a pixel electrode disposed on the organic layer and electrically connected to the drain electrode.

Abstract: A liquid crystal display including a display panel having data link lines, data lines, scan lines, and pixels connected to the data lines and the scan lines, a source drive integrated circuit configured to supply data voltages to the data lines via the data link lines, and a scan driver configured to provide scan signals to the scan lines. A p-th (p is a positive integer) data link line is connected to a (p+1)-th data line, and a (p+1)-th data link line is connected to a p-th data line.

Abstract: A display substrate includes a first switching element, an organic layer disposed on the first switching element, a capping layer disposed on the organic layer and a cover electrode covering the first emission hole. The first switching element is electrically connected to a gate line extending in a first direction, a data line extending in a second direction crossing the first direction and the pixel electrode disposed adjacent to the data line. The capping layer includes a first emission hole. The cover electrode overlaps the gate line as a first width. The cover electrode overlaps the first switching element as a second width. The second width is smaller than the first width.

Abstract: A display substrate includes a first gate line configured to receive a first gate clock, a second gate line adjacent to the first gate line and configured to receive a second gate clock, a first data line configured to transfer a first data signal inverted according to the first gate clock and the second gate clock, where the first data signal has a first polarity, a second data line configured to transfer a second data signal inverted according to the first gate clock and the second gate clock, where the second data signal has a second polarity different from the first polarity, a first pixel including a first high sub pixel electrically connected to the first gate line and the first data line, and a first low sub pixel electrically connected to the first gate line and the second data line.

Abstract: A thin film transistor array panel includes: first to third gate lines extending in one direction and parallel to each other; a data line insulated from and intersecting the first to third gate lines; a first thin film transistor connected to the first gate line and the data line; a second thin film transistor connected to the second gate line and an output terminal of the first thin film transistor; a third thin film transistor connected to the third gate line and the data line; a fourth thin film transistor connected to the second gate line and an output terminal of the third thin film transistor; and first to fourth sub-pixel electrodes respectively connected to the first to fourth thin film transistors.