Abstract: A method and a device for a chip layout, computer equipment, and a medium. The method includes steps of: determining external interfaces and internal interfaces of a chip, where the internal interface is a port of a component of the chip; constructing, according to the external interfaces and the internal interfaces, an objective function, where the objective function is applied to describe a wiring length of the chip; determining a target value of the objective function through a preset genetic algorithm, where the target value is applied to determine a first layout diagram of the chip; determining, based on an operation temperature of an internal chip as the component of the chip, a second layout diagram of the chip; performing an image fusion on the first layout diagram and the second layout diagram to obtain a target layout diagram of the chip.