Patents by Inventor Hongbo Rong

Hongbo Rong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150039861
    Abstract: In an embodiment, a system includes a processor including one or more cores and a plurality of alias registers to store memory range information associated with a plurality of operations of a loop. The memory range information references one or more memory locations within a memory. The system also includes register assignment means for assigning each of the alias registers to a corresponding operation of the loop, where the assignments are made according to a rotation schedule, and one of the alias registers is assigned to a first operation in a first iteration of the loop and to a second operation in a subsequent iteration of the loop. The system also includes the memory coupled to the processor. Other embodiments are described and claimed.
    Type: Application
    Filed: May 30, 2013
    Publication date: February 5, 2015
    Inventors: Hongbo Rong, Cheng Wang, Hyunchul Park, Youfeng Wu
  • Publication number: 20140359591
    Abstract: In an embodiment, a system includes a processor including at least one core to execute operations of a loop that includes S stages. The system also includes stage insertion means for adding a delay stage to the loop to increase a lifetime of a corresponding register associated with a first variable of the loop and to delay storage of contents of the register. The system also includes a dynamic random access memory (DRAM). Other embodiments are described and claimed.
    Type: Application
    Filed: May 30, 2013
    Publication date: December 4, 2014
    Inventors: Hyunchul Park, Hongbo Rong, Youfeng Wu
  • Publication number: 20140298306
    Abstract: Apparatuses and methods may provide for determining a level of performance for processing one or more loops by a dynamic compiler and executing code optimizations to generate a pipelined schedule for the one or more loops that achieves the determined level of performance within a prescribed time period. In one example, a dependence graph may be established for the one or more loops, and each dependence graph may be partitioned into stages based on the level of performance.
    Type: Application
    Filed: March 29, 2013
    Publication date: October 2, 2014
    Inventors: Hongbo Rong, Hyunchul Park, Youfeng Wu
  • Publication number: 20140208085
    Abstract: Logic and instruction to efficiently monitor loop trip count. Loop trip count information of a loop may be stored in a dedicated hardware buffer. Average loop trip count of the loop may be calculated based on the stored loop trip count information. Based on the average trip count, loop optimizations may be applied or removed from the loop. The stored loop trip count information may include an identifier identifying the loop, a total loop trip count of the loop, and an exit count of the loop.
    Type: Application
    Filed: March 30, 2012
    Publication date: July 24, 2014
    Inventors: Jaewoong Chung, Hyunchul Park, Hongbo Rong, Cheng Wang, Youfeng Wu
  • Patent number: 7631305
    Abstract: Methods and products for processing a software kernel of instructions are disclosed. The software kernel has stages representing a loop nest. The software kernel is processed by partitioning iterations of an outermost loop into groups with each group representing iterations of the outermost loop, running the software kernel and rotating a register file for each stage of the software kernel preceding an innermost loop to generate code to prepare for filling and executing instructions in software pipelines for a current group, running the software kernel for each stage of the software kernel in the innermost loop to generate code to fill the software pipelines for the current group with the register file being rotated after at least one run of the software kernel for the innermost loop, and repeatedly running the software kernel to unroll inner loops to generate code to further fill the software pipelines for the current group.
    Type: Grant
    Filed: September 20, 2004
    Date of Patent: December 8, 2009
    Assignee: University of Delaware
    Inventors: Hongbo Rong, Guang R. Gao, Alban Douillet, Ramaswamy Govindarajan
  • Publication number: 20050097509
    Abstract: Methods and products for processing a software kernel of instructions are disclosed. The software kernel has stages representing a loop nest. The software kernel is processed by partitioning iterations of an outermost loop into groups with each group representing iterations of the outermost loop, running the software kernel and rotating a register file for each stage of the software kernel preceding an innermost loop to generate code to prepare for filling and executing instructions in software pipelines for a current group, running the software kernel for each stage of the software kernel in the innermost loop to generate code to fill the software pipelines for the current group with the register file being rotated after at least one run of the software kernel for the innermost loop, and repeatedly running the software kernel to unroll inner loops to generate code to further fill the software pipelines for the current group.
    Type: Application
    Filed: September 20, 2004
    Publication date: May 5, 2005
    Inventors: Hongbo Rong, Guang Gao, Alban Douillet, Ramaswamy Govindarajan