Abstract: Construction of a T cell receptor and the use thereof are provided. Utilizing mutations of intracellular constant region sites of an ? chain and an ? chain of the T cell receptor to inhibit the degradation of the T cell receptor after TCR antigen signal activation, maintain the level of TCR on cell surface, and improve the efficacy of TCR-T cell therapy. This method can be applied to different TCR-T cell therapies.

Abstract: The present application discloses a manufacturing method of an optical film and the optical film. The manufacturing method includes: step S10, mixing titanium source precursors and a barium source and adding an alkaline agent for a reaction to obtain nanoparticles; and step S20, mixing quantum dots, an organic adhesive, and the nanoparticles followed by coating to obtain the optical film.

Abstract: A power conversion circuit includes a transconductance amplifier circuit, a current limiting circuit, and a controller. The transconductance amplifier circuit is configured to provide a first output current at a first output based on a differential between a first voltage at the first input and a second voltage at a second input. The current limiting circuit is configured to provide a second output current at the second output that is an input current at a third input limited to no greater than the first output current. The controller is configured to control first and second switches during a time period where the power conversion circuit transitions between an active mode and a skip mode.

Abstract: Described embodiments include a circuit with a first amplifier having first and second amplifier inputs and a first amplifier output. The first amplifier input is coupled to a reference voltage terminal. The second amplifier input is coupled to a voltage feedback terminal. A second amplifier has third and fourth amplifier inputs and second and third amplifier outputs. The third amplifier input is coupled to the first amplifier output. A first switch has first and second switch terminals. The second switch terminal is coupled to the fourth amplifier input. A third amplifier has fifth and sixth amplifier inputs and a fourth amplifier output. The fifth amplifier input is coupled to the second amplifier output. The sixth amplifier input is coupled to the third amplifier output. A second switch has a third switch terminal coupled to the fourth amplifier output, and a fourth switch terminal coupled to the first amplifier output.

Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. The first transistor comprises a drain terminal coupled to an input voltage node, a source terminal coupled to a first node, and a gate terminal coupled to a second node. The second transistor comprises a drain terminal coupled to a third node, a source terminal coupled to a fourth node, and a gate terminal coupled to a fifth node. The third transistor comprises a drain terminal coupled to a sixth node, a source terminal configured to couple to a gate terminal of a switching transistor, and a gate terminal coupled to a seventh node. The first capacitor is coupled between the first node and the third node. The second capacitor is coupled between the fourth node and the sixth node.

Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. The first transistor comprises a drain terminal coupled to an input voltage node, a source terminal coupled to a first node, and a gate terminal coupled to a second node. The second transistor comprises a drain terminal coupled to a third node, a source terminal coupled to a fourth node, and a gate terminal coupled to a fifth node. The third transistor comprises a drain terminal coupled to a sixth node, a source terminal configured to couple to a gate terminal of a switching transistor, and a gate terminal coupled to a seventh node. The first capacitor is coupled between the first node and the third node. The second capacitor is coupled between the fourth node and the sixth node.

Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. The first transistor comprises a drain terminal coupled to an input voltage node, a source terminal coupled to a first node, and a gate terminal coupled to a second node. The second transistor comprises a drain terminal coupled to a third node, a source terminal coupled to a fourth node, and a gate terminal coupled to a fifth node. The third transistor comprises a drain terminal coupled to a sixth node, a source terminal configured to couple to a gate terminal of a switching transistor, and a gate terminal coupled to a seventh node. The first capacitor is coupled between the first node and the third node. The second capacitor is coupled between the fourth node and the sixth node.

Abstract: The present disclosure relates to template data processing, template data requesting, and template data presenting methods and devices, and a storage medium. The method includes obtaining a template subject and template key words matching the template subject and generating, according to the template key words, a first template message matching the template subject. The first template message includes the template key words. The method also includes generating a template identifier corresponding to the first template message and associating the template identifier with the corresponding first template message. The method further includes storing the template identifier and the corresponding first template message into a template library.

Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. The first transistor comprises a drain terminal coupled to an input voltage node, a source terminal coupled to a first node, and a gate terminal coupled to a second node. The second transistor comprises a drain terminal coupled to a third node, a source terminal coupled to a fourth node, and a gate terminal coupled to a fifth node. The third transistor comprises a drain terminal coupled to a sixth node, a source terminal configured to couple to a gate terminal of a switching transistor, and a gate terminal coupled to a seventh node. The first capacitor is coupled between the first node and the third node. The second capacitor is coupled between the fourth node and the sixth node.

Abstract: The present disclosure relates to template data processing, template data requesting, and template data presenting methods and devices, and a storage medium. The method includes obtaining a template subject and template key words matching the template subject and generating, according to the template key words, a first template message matching the template subject. The first template message includes the template key words. The method also includes generating a template identifier corresponding to the first template message and associating the template identifier with the corresponding first template message. The method further includes storing the template identifier and the corresponding first template message into a template library.